2015-08-01 19:35:18 +00:00
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/*
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* Copyright (C) 2015 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/arch/sdram.h>
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/* QTS output file. */
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#include "qts/sdram_config.h"
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2015-08-02 15:15:19 +00:00
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#include "qts/sequencer_auto_ac_init.h"
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#include "qts/sequencer_auto_inst_init.h"
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2015-08-01 19:35:18 +00:00
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static const struct socfpga_sdram_config sdram_config = {
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.ctrl_cfg =
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
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SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
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SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
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SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
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SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
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SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
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SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
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SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
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SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
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SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
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.dram_timing1 =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
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SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
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SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
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SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
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SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
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SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
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SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
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.dram_timing2 =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
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SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
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SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
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SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
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SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
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SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
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.dram_timing3 =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
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SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
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SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
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SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
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SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
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SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
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.dram_timing4 =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
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SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
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SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
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.lowpwr_timing =
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(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
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SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
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SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
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.dram_odt =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
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SDR_CTRLGRP_DRAMODT_READ_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
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SDR_CTRLGRP_DRAMODT_WRITE_LSB),
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.dram_addrw =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
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SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
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SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
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SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
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((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
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SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
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.dram_if_width =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
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SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
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.dram_dev_width =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
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SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
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.dram_intr =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
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SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
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.lowpwr_eq =
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(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
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SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
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.static_cfg =
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(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
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SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
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SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
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.ctrl_width =
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(CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
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SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
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.cport_width =
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(CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
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SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
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.cport_wmap =
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(CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
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SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
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.cport_rmap =
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(CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
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SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
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.rfifo_cmap =
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(CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
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SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
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.wfifo_cmap =
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(CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
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SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
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.cport_rdwr =
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(CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
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SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
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.port_cfg =
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(CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
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SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
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.fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
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.fifo_cfg =
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(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
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SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
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SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
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.mp_priority =
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(CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
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SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
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.mp_weight0 =
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
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.mp_weight1 =
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
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.mp_weight2 =
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
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.mp_weight3 =
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
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.mp_pacing0 =
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
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SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
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.mp_pacing1 =
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
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SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
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SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
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.mp_pacing2 =
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
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SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
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.mp_pacing3 =
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
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SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
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.mp_threshold0 =
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(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
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SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
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.mp_threshold1 =
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(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
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SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
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.mp_threshold2 =
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(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
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SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
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.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
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};
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const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
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{
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return &sdram_config;
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}
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2015-08-02 15:15:19 +00:00
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void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem)
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{
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*init = ac_rom_init;
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*nelem = ARRAY_SIZE(ac_rom_init);
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}
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void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
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{
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*init = inst_rom_init;
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*nelem = ARRAY_SIZE(inst_rom_init);
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}
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