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u-boot/drivers/misc/fsl_ifc.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-20 10:59:35 +00:00
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* Author: Dipen Dudhat <dipen.dudhat@freescale.com>
*/
#include <common.h>
Driver/IFC: Move Freescale IFC driver to a common driver Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com>
2013-10-22 19:39:02 +00:00
#include <fsl_ifc.h>
common: Drop part.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:39:58 +00:00
#include <part.h>
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-20 10:59:35 +00:00
drivers: ifc: restore the legacy flow for IFC config Restore the legacy flow along with TFABOOT flow for IFC configuration. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-27 04:37:51 +00:00
#ifdef CONFIG_TFABOOT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"cs0",
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-20 10:59:35 +00:00
#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSPR0,
Added new ext fields to IFC In case more than 32 bit address is used, the EXT bit should be set. Need to fix up address map for IFC #CS for 4, also need to move # of IFC banks into config_mpc85xx.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:25 +00:00
#ifdef CONFIG_SYS_CSPR0_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSPR0_EXT,
#else
0,
#endif
#ifdef CONFIG_SYS_AMASK0
CONFIG_SYS_AMASK0,
#else
0,
#endif
CONFIG_SYS_CSOR0,
{
CONFIG_SYS_CS0_FTIM0,
CONFIG_SYS_CS0_FTIM1,
CONFIG_SYS_CS0_FTIM2,
CONFIG_SYS_CS0_FTIM3,
},
mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-10-04 04:35:36 +00:00
#ifdef CONFIG_SYS_CSOR0_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSOR0_EXT,
#else
0,
#endif
#ifdef CONFIG_SYS_CSPR0_FINAL
CONFIG_SYS_CSPR0_FINAL,
#else
0,
Added new ext fields to IFC In case more than 32 bit address is used, the EXT bit should be set. Need to fix up address map for IFC #CS for 4, also need to move # of IFC banks into config_mpc85xx.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:25 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#ifdef CONFIG_SYS_AMASK0_FINAL
CONFIG_SYS_AMASK0_FINAL,
#else
0,
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-20 10:59:35 +00:00
#endif
fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010) Issue: Address masking doesn't work properly. When sum of the base address, defined by BA, and memory bank size, defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask CSPRn[BA] bits. Impact: This will impact booting when we are reprogramming CSPR0(BA) and AMASK0(AMASK) while executing from NOR Flash. Workaround: Re-programming of CSPR(BA) and AMASK is done while not executing from NOR Flash. The code which programs the BA and AMASK is executed from L2-SRAM. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-07 15:06:47 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
},
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-20 10:59:35 +00:00
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 2
{
"cs1",
#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
CONFIG_SYS_CSPR1,
Added new ext fields to IFC In case more than 32 bit address is used, the EXT bit should be set. Need to fix up address map for IFC #CS for 4, also need to move # of IFC banks into config_mpc85xx.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:25 +00:00
#ifdef CONFIG_SYS_CSPR1_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSPR1_EXT,
#else
0,
#endif
#ifdef CONFIG_SYS_AMASK1
CONFIG_SYS_AMASK1,
#else
0,
#endif
CONFIG_SYS_CSOR1,
{
CONFIG_SYS_CS1_FTIM0,
CONFIG_SYS_CS1_FTIM1,
CONFIG_SYS_CS1_FTIM2,
CONFIG_SYS_CS1_FTIM3,
},
mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-10-04 04:35:36 +00:00
#ifdef CONFIG_SYS_CSOR1_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSOR1_EXT,
#else
0,
mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-10-04 04:35:36 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#ifdef CONFIG_SYS_CSPR1_FINAL
CONFIG_SYS_CSPR1_FINAL,
#else
0,
#endif
#ifdef CONFIG_SYS_AMASK1_FINAL
CONFIG_SYS_AMASK1_FINAL,
#else
0,
#endif
#endif
},
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-20 10:59:35 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 3
{
"cs2",
#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
CONFIG_SYS_CSPR2,
Added new ext fields to IFC In case more than 32 bit address is used, the EXT bit should be set. Need to fix up address map for IFC #CS for 4, also need to move # of IFC banks into config_mpc85xx.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:25 +00:00
#ifdef CONFIG_SYS_CSPR2_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSPR2_EXT,
#else
0,
#endif
#ifdef CONFIG_SYS_AMASK2
CONFIG_SYS_AMASK2,
#else
0,
#endif
CONFIG_SYS_CSOR2,
{
CONFIG_SYS_CS2_FTIM0,
CONFIG_SYS_CS2_FTIM1,
CONFIG_SYS_CS2_FTIM2,
CONFIG_SYS_CS2_FTIM3,
},
mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-10-04 04:35:36 +00:00
#ifdef CONFIG_SYS_CSOR2_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSOR2_EXT,
#else
0,
#endif
#ifdef CONFIG_SYS_CSPR2_FINAL
CONFIG_SYS_CSPR2_FINAL,
#else
0,
#endif
#ifdef CONFIG_SYS_AMASK2_FINAL
CONFIG_SYS_AMASK2_FINAL,
#else
0,
mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-10-04 04:35:36 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#endif
},
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-20 10:59:35 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 4
{
"cs3",
#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
CONFIG_SYS_CSPR3,
Added new ext fields to IFC In case more than 32 bit address is used, the EXT bit should be set. Need to fix up address map for IFC #CS for 4, also need to move # of IFC banks into config_mpc85xx.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:25 +00:00
#ifdef CONFIG_SYS_CSPR3_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSPR3_EXT,
#else
0,
#endif
#ifdef CONFIG_SYS_AMASK3
CONFIG_SYS_AMASK3,
#else
0,
#endif
CONFIG_SYS_CSOR3,
{
CONFIG_SYS_CS3_FTIM0,
CONFIG_SYS_CS3_FTIM1,
CONFIG_SYS_CS3_FTIM2,
CONFIG_SYS_CS3_FTIM3,
},
mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-10-04 04:35:36 +00:00
#ifdef CONFIG_SYS_CSOR3_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSOR3_EXT,
#else
0,
#endif
#ifdef CONFIG_SYS_CSPR3_FINAL
CONFIG_SYS_CSPR3_FINAL,
#else
0,
#endif
#ifdef CONFIG_SYS_AMASK3_FINAL
CONFIG_SYS_AMASK3_FINAL,
#else
0,
mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-10-04 04:35:36 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#endif
},
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-20 10:59:35 +00:00
#endif
fsl_ifc: add support for different IFC bank count Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-16 02:18:13 +00:00
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 5
{
"cs4",
#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
CONFIG_SYS_CSPR4,
fsl_ifc: add support for different IFC bank count Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-16 02:18:13 +00:00
#ifdef CONFIG_SYS_CSPR4_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSPR4_EXT,
#else
0,
#endif
#ifdef CONFIG_SYS_AMASK4
CONFIG_SYS_AMASK4,
#else
0,
#endif
CONFIG_SYS_CSOR4,
{
CONFIG_SYS_CS4_FTIM0,
CONFIG_SYS_CS4_FTIM1,
CONFIG_SYS_CS4_FTIM2,
CONFIG_SYS_CS4_FTIM3,
},
mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-10-04 04:35:36 +00:00
#ifdef CONFIG_SYS_CSOR4_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSOR4_EXT,
#else
0,
mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-10-04 04:35:36 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#ifdef CONFIG_SYS_CSPR4_FINAL
CONFIG_SYS_CSPR4_FINAL,
#else
0,
#endif
#ifdef CONFIG_SYS_AMASK4_FINAL
CONFIG_SYS_AMASK4_FINAL,
#else
0,
#endif
#endif
},
fsl_ifc: add support for different IFC bank count Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-16 02:18:13 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 6
{
"cs5",
#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
CONFIG_SYS_CSPR5,
fsl_ifc: add support for different IFC bank count Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-16 02:18:13 +00:00
#ifdef CONFIG_SYS_CSPR5_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSPR5_EXT,
#else
0,
#endif
#ifdef CONFIG_SYS_AMASK5
CONFIG_SYS_AMASK5,
#else
0,
#endif
CONFIG_SYS_CSOR5,
{
CONFIG_SYS_CS5_FTIM0,
CONFIG_SYS_CS5_FTIM1,
CONFIG_SYS_CS5_FTIM2,
CONFIG_SYS_CS5_FTIM3,
},
mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-10-04 04:35:36 +00:00
#ifdef CONFIG_SYS_CSOR5_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSOR5_EXT,
#else
0,
mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-10-04 04:35:36 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#ifdef CONFIG_SYS_CSPR5_FINAL
CONFIG_SYS_CSPR5_FINAL,
#else
0,
#endif
#ifdef CONFIG_SYS_AMASK5_FINAL
CONFIG_SYS_AMASK5_FINAL,
#else
0,
#endif
#endif
},
fsl_ifc: add support for different IFC bank count Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-16 02:18:13 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 7
{
"cs6",
#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
CONFIG_SYS_CSPR6,
fsl_ifc: add support for different IFC bank count Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-16 02:18:13 +00:00
#ifdef CONFIG_SYS_CSPR6_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSPR6_EXT,
#else
0,
#endif
#ifdef CONFIG_SYS_AMASK6
CONFIG_SYS_AMASK6,
#else
0,
#endif
CONFIG_SYS_CSOR6,
{
CONFIG_SYS_CS6_FTIM0,
CONFIG_SYS_CS6_FTIM1,
CONFIG_SYS_CS6_FTIM2,
CONFIG_SYS_CS6_FTIM3,
},
mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-10-04 04:35:36 +00:00
#ifdef CONFIG_SYS_CSOR6_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSOR6_EXT,
#else
0,
mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-10-04 04:35:36 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#ifdef CONFIG_SYS_CSPR6_FINAL
CONFIG_SYS_CSPR6_FINAL,
#else
0,
#endif
#ifdef CONFIG_SYS_AMASK6_FINAL
CONFIG_SYS_AMASK6_FINAL,
#else
0,
#endif
#endif
},
fsl_ifc: add support for different IFC bank count Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-16 02:18:13 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 8
{
"cs7",
#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
CONFIG_SYS_CSPR7,
fsl_ifc: add support for different IFC bank count Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-16 02:18:13 +00:00
#ifdef CONFIG_SYS_CSPR7_EXT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSPR7_EXT,
#else
0,
fsl_ifc: add support for different IFC bank count Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-16 02:18:13 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
#ifdef CONFIG_SYS_AMASK7
CONFIG_SYS_AMASK7,
#else
0,
mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-10-04 04:35:36 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
CONFIG_SYS_CSOR7,
#ifdef CONFIG_SYS_CSOR7_EXT
CONFIG_SYS_CSOR7_EXT,
#else
0,
#endif
{
CONFIG_SYS_CS7_FTIM0,
CONFIG_SYS_CS7_FTIM1,
CONFIG_SYS_CS7_FTIM2,
CONFIG_SYS_CS7_FTIM3,
},
#ifdef CONFIG_SYS_CSPR7_FINAL
CONFIG_SYS_CSPR7_FINAL,
#else
0,
#endif
#ifdef CONFIG_SYS_AMASK7_FINAL
CONFIG_SYS_AMASK7_FINAL,
#else
0,
#endif
#endif
},
#endif
};
fsl_ifc: add support for different IFC bank count Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-16 02:18:13 +00:00
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
__weak void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
{
regs_info->regs = ifc_cfg_default_boot;
regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
}
drivers: ifc: restore the legacy flow for IFC config Restore the legacy flow along with TFABOOT flow for IFC configuration. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-27 04:37:51 +00:00
#endif
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
void print_ifc_regs(void)
{
int i, j;
printf("IFC Controller Registers\n");
for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
i, get_ifc_cspr(i), i, get_ifc_amask(i),
i, get_ifc_csor(i));
for (j = 0; j < 4; j++)
printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j));
}
}
drivers: ifc: restore the legacy flow for IFC config Restore the legacy flow along with TFABOOT flow for IFC configuration. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-27 04:37:51 +00:00
#ifdef CONFIG_TFABOOT
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
void init_early_memctl_regs(void)
{
int i, j;
struct ifc_regs *regs;
struct ifc_regs_info regs_info = {0};
ifc_cfg_boot_info(&regs_info);
regs = regs_info.regs;
for (i = 0 ; i < regs_info.cs_size; i++) {
if (regs[i].pr && (regs[i].pr & CSPR_V)) {
/* skip setting cspr/csor_ext in below condition */
if (!(CONFIG_IS_ENABLED(A003399_NOR_WORKAROUND) &&
i == 0 &&
((regs[0].pr & CSPR_MSEL) == CSPR_MSEL_NOR))) {
if (regs[i].pr_ext)
set_ifc_cspr_ext(i, regs[i].pr_ext);
if (regs[i].or_ext)
set_ifc_csor_ext(i, regs[i].or_ext);
}
for (j = 0; j < ARRAY_SIZE(regs->ftim); j++)
set_ifc_ftim(i, j, regs[i].ftim[j]);
set_ifc_csor(i, regs[i].or);
set_ifc_amask(i, regs[i].amask);
set_ifc_cspr(i, regs[i].pr);
}
}
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-20 10:59:35 +00:00
}
driver/fsl_ifc: Add a function to finalize CS0 address binding For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded to higher address to support large space. Signed-off-by: York Sun <yorksun@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-03-19 20:52:34 +00:00
void init_final_memctl_regs(void)
{
drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:33 +00:00
int i;
struct ifc_regs *regs;
struct ifc_regs_info regs_info;
ifc_cfg_boot_info(&regs_info);
regs = regs_info.regs;
for (i = 0 ; i < regs_info.cs_size && i < ARRAY_SIZE(regs->ftim); i++) {
if (!(regs[i].pr_final & CSPR_V))
continue;
if (regs[i].pr_final)
set_ifc_cspr(i, regs[i].pr_final);
if (regs[i].amask_final)
set_ifc_amask(i, (i == 1) ? regs[i].amask_final :
regs[i].amask);
}
driver/fsl_ifc: Add a function to finalize CS0 address binding For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded to higher address to support large space. Signed-off-by: York Sun <yorksun@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-03-19 20:52:34 +00:00
}
drivers: ifc: restore the legacy flow for IFC config Restore the legacy flow along with TFABOOT flow for IFC configuration. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-27 04:37:51 +00:00
#else
void init_early_memctl_regs(void)
{
#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
#ifndef CONFIG_A003399_NOR_WORKAROUND
#ifdef CONFIG_SYS_CSPR0_EXT
set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
#endif
#ifdef CONFIG_SYS_CSOR0_EXT
set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT);
#endif
set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
#endif
#endif
#ifdef CONFIG_SYS_CSPR1_EXT
set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
#endif
#ifdef CONFIG_SYS_CSOR1_EXT
set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT);
#endif
#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
#endif
#ifdef CONFIG_SYS_CSPR2_EXT
set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
#endif
#ifdef CONFIG_SYS_CSOR2_EXT
set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT);
#endif
#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2);
set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3);
set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
#endif
#ifdef CONFIG_SYS_CSPR3_EXT
set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
#endif
#ifdef CONFIG_SYS_CSOR3_EXT
set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT);
#endif
#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2);
set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3);
set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
#endif
#ifdef CONFIG_SYS_CSPR4_EXT
set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
#endif
#ifdef CONFIG_SYS_CSOR4_EXT
set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT);
#endif
#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
#endif
#ifdef CONFIG_SYS_CSPR5_EXT
set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
#endif
#ifdef CONFIG_SYS_CSOR5_EXT
set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT);
#endif
#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
#endif
#ifdef CONFIG_SYS_CSPR6_EXT
set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
#endif
#ifdef CONFIG_SYS_CSOR6_EXT
set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT);
#endif
#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
#endif
#ifdef CONFIG_SYS_CSPR7_EXT
set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
#endif
#ifdef CONFIG_SYS_CSOR7_EXT
set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT);
#endif
#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
#endif
}
void init_final_memctl_regs(void)
{
#ifdef CONFIG_SYS_CSPR0_FINAL
set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
#endif
#ifdef CONFIG_SYS_AMASK0_FINAL
set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
#endif
#ifdef CONFIG_SYS_CSPR1_FINAL
set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL);
#endif
#ifdef CONFIG_SYS_AMASK1_FINAL
set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL);
#endif
#ifdef CONFIG_SYS_CSPR2_FINAL
set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL);
#endif
#ifdef CONFIG_SYS_AMASK2_FINAL
set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
#endif
#ifdef CONFIG_SYS_CSPR3_FINAL
set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL);
#endif
#ifdef CONFIG_SYS_AMASK3_FINAL
set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
#endif
}
#endif
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