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60 lines
1.5 KiB
C
60 lines
1.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2018 Xilinx, Inc.
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* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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*
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* Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG <oss@weidmueller.com>
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* Christian Taedcke <christian.taedcke@weidmueller.com>
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*/
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#include <common.h>
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#include <mach/zynqmp_aes.h>
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#include <asm/arch/sys_proto.h>
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#include <cpu_func.h>
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#include <memalign.h>
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#include <zynqmp_firmware.h>
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int zynqmp_aes_operation(struct zynqmp_aes *aes)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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if (zynqmp_firmware_version() <= PMUFW_V1_0)
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return -ENOENT;
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if (aes->srcaddr && aes->ivaddr && aes->dstaddr) {
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flush_dcache_range(aes->srcaddr,
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aes->srcaddr +
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roundup(aes->len, ARCH_DMA_MINALIGN));
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flush_dcache_range(aes->ivaddr,
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aes->ivaddr +
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roundup(IV_SIZE, ARCH_DMA_MINALIGN));
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flush_dcache_range(aes->dstaddr,
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aes->dstaddr +
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roundup(aes->len, ARCH_DMA_MINALIGN));
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}
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if (aes->keysrc == 0) {
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if (aes->keyaddr == 0)
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return -EINVAL;
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flush_dcache_range(aes->keyaddr,
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aes->keyaddr +
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roundup(KEY_PTR_LEN, ARCH_DMA_MINALIGN));
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}
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flush_dcache_range((ulong)aes, (ulong)(aes) +
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roundup(sizeof(struct zynqmp_aes), ARCH_DMA_MINALIGN));
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ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes),
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lower_32_bits((ulong)aes), 0, 0, ret_payload);
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if (ret || ret_payload[1]) {
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printf("Failed: AES op status:0x%x, errcode:0x%x\n",
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ret, ret_payload[1]);
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return -EIO;
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}
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return 0;
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}
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