2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2014-05-05 13:42:31 +00:00
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/*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Aaron <leafy.myeh@allwinnertech.com>
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*
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* MMC register definition for allwinner sunxi platform.
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*/
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#ifndef _SUNXI_MMC_H
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#define _SUNXI_MMC_H
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#include <linux/types.h>
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struct sunxi_mmc {
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u32 gctrl; /* 0x00 global control */
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u32 clkcr; /* 0x04 clock control */
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u32 timeout; /* 0x08 time out */
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u32 width; /* 0x0c bus width */
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u32 blksz; /* 0x10 block size */
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u32 bytecnt; /* 0x14 byte count */
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u32 cmd; /* 0x18 command */
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u32 arg; /* 0x1c argument */
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u32 resp0; /* 0x20 response 0 */
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u32 resp1; /* 0x24 response 1 */
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u32 resp2; /* 0x28 response 2 */
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u32 resp3; /* 0x2c response 3 */
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u32 imask; /* 0x30 interrupt mask */
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u32 mint; /* 0x34 masked interrupt status */
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u32 rint; /* 0x38 raw interrupt status */
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u32 status; /* 0x3c status */
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u32 ftrglevel; /* 0x40 FIFO threshold watermark*/
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u32 funcsel; /* 0x44 function select */
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u32 cbcr; /* 0x48 CIU byte count */
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u32 bbcr; /* 0x4c BIU byte count */
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u32 dbgc; /* 0x50 debug enable */
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2017-08-23 10:03:41 +00:00
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u32 res0; /* 0x54 reserved */
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u32 a12a; /* 0x58 Auto command 12 argument */
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u32 ntsr; /* 0x5c New timing set register */
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u32 res1[8];
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2014-05-05 13:42:31 +00:00
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u32 dmac; /* 0x80 internal DMA control */
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u32 dlba; /* 0x84 internal DMA descr list base address */
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u32 idst; /* 0x88 internal DMA status */
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u32 idie; /* 0x8c internal DMA interrupt enable */
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u32 chda; /* 0x90 */
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u32 cbda; /* 0x94 */
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2017-08-23 10:03:41 +00:00
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u32 res2[26];
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2021-01-11 20:11:35 +00:00
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#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
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2018-11-06 04:24:28 +00:00
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u32 res3[17];
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u32 samp_dl;
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u32 res4[46];
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2014-10-03 12:16:26 +00:00
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#endif
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2015-01-14 18:05:03 +00:00
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u32 fifo; /* 0x100 / 0x200 FIFO access address */
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2014-05-05 13:42:31 +00:00
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};
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#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
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#define SUNXI_MMC_CLK_ENABLE (0x1 << 16)
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#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff)
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#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0)
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#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1)
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#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2)
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#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\
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SUNXI_MMC_GCTRL_FIFO_RESET|\
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SUNXI_MMC_GCTRL_DMA_RESET)
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#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5)
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#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31)
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#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6)
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#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7)
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#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8)
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#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9)
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#define SUNXI_MMC_CMD_WRITE (0x1 << 10)
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#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12)
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#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13)
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#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15)
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#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21)
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#define SUNXI_MMC_CMD_START (0x1 << 31)
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#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1)
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#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2)
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#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3)
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#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4)
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#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5)
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#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6)
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#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7)
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#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8)
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#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9)
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#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10)
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#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11)
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#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12)
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#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13)
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#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14)
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#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15)
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#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16)
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#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30)
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#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31)
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#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \
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(SUNXI_MMC_RINT_RESP_ERROR | \
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SUNXI_MMC_RINT_RESP_CRC_ERROR | \
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SUNXI_MMC_RINT_DATA_CRC_ERROR | \
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SUNXI_MMC_RINT_RESP_TIMEOUT | \
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SUNXI_MMC_RINT_DATA_TIMEOUT | \
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SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \
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SUNXI_MMC_RINT_FIFO_RUN_ERROR | \
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SUNXI_MMC_RINT_HARD_WARE_LOCKED | \
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SUNXI_MMC_RINT_START_BIT_ERROR | \
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SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
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#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \
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(SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \
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SUNXI_MMC_RINT_DATA_OVER | \
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SUNXI_MMC_RINT_COMMAND_DONE | \
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SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
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#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0)
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#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1)
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#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2)
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#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3)
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#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8)
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#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9)
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#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10)
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mmc: sunxi: Increase MMIO FIFO read performance
To avoid the complexity of DMA operations (with chained descriptors), we
use repeated MMIO reads and writes to the SD_FIFO_REG, which allows us
to drain or fill the MMC data buffer FIFO very easily.
However those MMIO accesses are somewhat costly, so this limits our MMC
performance, to between 17 and 22 MB/s, but down to 9.5 MB/s on the H6
(partly due to the lower AHB1 frequency).
As it turns out we read the FIFO status register after *every* word we
read or write, which effectively doubles the number of MMIO accesses,
thus effectively more than halving our performance.
To avoid this overhead, we can make use of the FIFO level bits, which are
in the very same FIFO status registers.
So for a read request, we now can collect as many words as the FIFO
level originally indicated, and only then need to update the status
register.
We don't know for sure the size of the FIFO (and it seems to differ
across SoCs anyway), so writing is more fragile, which is why we still
use the old method for that. If we find a minimum FIFO size available on
all SoCs, we could use that, in a later optimisation.
This patch increases the eMMC read speed on a Pine64-LTS from about
22MB/s to 44 MB/s. SD card reads don't gain that much, but with 23 MB/s
we now reach the practical limit for 3.3V SD cards.
On the H6 we double our transfer speed, from 9.5 MB/s to 19.7 MB/s.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-05-05 10:33:40 +00:00
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#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff)
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2014-05-05 13:42:31 +00:00
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2017-08-23 10:03:41 +00:00
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#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
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2014-05-05 13:42:31 +00:00
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#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
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#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
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#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
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#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
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#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
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2015-01-14 18:05:03 +00:00
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#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
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#define SUNXI_MMC_COMMON_RESET (1 << 18)
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2018-11-06 04:24:28 +00:00
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#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
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2014-10-02 19:13:54 +00:00
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struct mmc *sunxi_mmc_init(int sdc_no);
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2014-05-05 13:42:31 +00:00
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#endif /* _SUNXI_MMC_H */
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