u-boot/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 18
 *
 * Some assumptions are made:
 *    * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4)
 *    * mezzanine card M13/M8 is connected to IO SLOT6 (25g-aui for DPMAC 5,6)
 *
 * Copyright 2020-2021 NXP
 *
 */

#include "fsl-lx2160a-qds.dtsi"

&dpmac3 {
	status = "okay";
	phy-handle = <&aquantia_phy1>;
	phy-connection-type = "usxgmii";
};

&dpmac4 {
	status = "okay";
	phy-handle = <&aquantia_phy2>;
	phy-connection-type = "usxgmii";
};

&dpmac5 {
	status = "okay";
	phy-handle = <&inphi_phy0>;
	phy-connection-type = "25g-aui";
};

&dpmac6 {
	status = "okay";
	phy-handle = <&inphi_phy1>;
	phy-connection-type = "25g-aui";
};

&emdio1_slot1 {
	aquantia_phy1: ethernet-phy@4 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <0x0>;
	};

	aquantia_phy2: ethernet-phy@5 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <0x1>;
	};
};

&emdio1_slot6 {
	inphi_phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-id0210.7440";
		reg = <0x0>;
	};

	inphi_phy1: ethernet-phy@1 {
		compatible = "ethernet-phy-id0210.7440";
		reg = <0x1>;
	};
};

&esdhc1 {
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	bus-width = <8>;
};