2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2011-11-08 23:18:09 +00:00
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/*
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* Freescale i.MX28 SSP MMC driver
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*
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2019-09-05 07:54:59 +00:00
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* Copyright (C) 2019 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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2011-11-08 23:18:09 +00:00
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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* Terry Lv
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*
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* Copyright 2007, Freescale Semiconductor, Inc
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* Andy Fleming
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*
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* Based vaguely on the pxa mmc code:
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* (C) Copyright 2003
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*/
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2019-09-05 07:54:59 +00:00
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2011-11-08 23:18:09 +00:00
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#include <common.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2011-11-08 23:18:09 +00:00
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#include <malloc.h>
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#include <mmc.h>
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2020-05-10 17:40:13 +00:00
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#include <linux/bitops.h>
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2020-05-10 17:40:11 +00:00
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#include <linux/delay.h>
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2016-09-21 02:28:55 +00:00
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#include <linux/errno.h>
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2011-11-08 23:18:09 +00:00
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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2017-06-29 08:16:06 +00:00
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#include <asm/mach-imx/dma.h>
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2012-08-26 15:19:07 +00:00
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#include <bouncebuf.h>
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2011-11-08 23:18:09 +00:00
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2019-09-05 07:54:59 +00:00
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#define MXSMMC_MAX_TIMEOUT 10000
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#define MXSMMC_SMALL_TRANSFER 512
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#if !CONFIG_IS_ENABLED(DM_MMC)
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2011-11-08 23:18:09 +00:00
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struct mxsmmc_priv {
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int id;
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int (*mmc_is_wp)(int);
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2013-01-22 15:01:03 +00:00
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int (*mmc_cd)(int);
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2014-03-11 17:34:20 +00:00
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struct mmc_config cfg; /* mmc configuration */
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2019-09-05 07:54:59 +00:00
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struct mxs_dma_desc *desc;
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uint32_t buswidth;
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struct mxs_ssp_regs *regs;
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2011-11-08 23:18:09 +00:00
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};
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2019-09-05 07:54:59 +00:00
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#else /* CONFIG_IS_ENABLED(DM_MMC) */
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#include <dm/device.h>
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#include <dm/read.h>
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#include <dt-structs.h>
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#ifdef CONFIG_MX28
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#define dtd_fsl_imx_mmc dtd_fsl_imx28_mmc
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#else /* CONFIG_MX23 */
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#define dtd_fsl_imx_mmc dtd_fsl_imx23_mmc
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#endif
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2011-11-08 23:18:09 +00:00
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2019-09-05 07:54:59 +00:00
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struct mxsmmc_platdata {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_fsl_imx_mmc dtplat;
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#endif
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struct mmc_config cfg;
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struct mmc mmc;
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fdt_addr_t base;
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int non_removable;
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int buswidth;
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int dma_id;
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int clk_id;
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};
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struct mxsmmc_priv {
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int clkid;
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struct mxs_dma_desc *desc;
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u32 buswidth;
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struct mxs_ssp_regs *regs;
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unsigned int dma_channel;
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};
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#endif
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#if !CONFIG_IS_ENABLED(DM_MMC)
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static int mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data);
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2011-11-08 23:18:09 +00:00
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2013-01-22 15:01:03 +00:00
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static int mxsmmc_cd(struct mxsmmc_priv *priv)
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{
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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if (priv->mmc_cd)
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return priv->mmc_cd(priv->id);
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return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
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}
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2019-09-05 07:54:59 +00:00
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static int mxsmmc_set_ios(struct mmc *mmc)
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{
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struct mxsmmc_priv *priv = mmc->priv;
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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/* Set the clock speed */
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if (mmc->clock)
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mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
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switch (mmc->bus_width) {
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case 1:
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priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
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break;
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case 4:
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priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
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break;
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case 8:
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priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
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break;
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}
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/* Set the bus width */
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clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
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SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
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debug("MMC%d: Set %d bits bus width\n",
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mmc->block_dev.devnum, mmc->bus_width);
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return 0;
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}
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static int mxsmmc_init(struct mmc *mmc)
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{
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struct mxsmmc_priv *priv = mmc->priv;
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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/* Reset SSP */
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mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
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/* Reconfigure the SSP block for MMC operation */
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writel(SSP_CTRL1_SSP_MODE_SD_MMC |
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SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
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SSP_CTRL1_DMA_ENABLE |
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SSP_CTRL1_POLARITY |
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SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
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SSP_CTRL1_DATA_CRC_IRQ_EN |
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SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
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SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
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SSP_CTRL1_RESP_ERR_IRQ_EN,
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&ssp_regs->hw_ssp_ctrl1_set);
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/* Set initial bit clock 400 KHz */
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mxs_set_ssp_busclock(priv->id, 400);
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/* Send initial 74 clock cycles (185 us @ 400 KHz)*/
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writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
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udelay(200);
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writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
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return 0;
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}
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static const struct mmc_ops mxsmmc_ops = {
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.send_cmd = mxsmmc_send_cmd,
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.set_ios = mxsmmc_set_ios,
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.init = mxsmmc_init,
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};
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2020-06-26 06:13:33 +00:00
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int mxsmmc_initialize(struct bd_info *bis, int id, int (*wp)(int),
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int (*cd)(int))
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2019-09-05 07:54:59 +00:00
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{
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struct mmc *mmc = NULL;
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struct mxsmmc_priv *priv = NULL;
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int ret;
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const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
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if (!mxs_ssp_bus_id_valid(id))
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return -ENODEV;
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priv = malloc(sizeof(struct mxsmmc_priv));
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if (!priv)
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return -ENOMEM;
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priv->desc = mxs_dma_desc_alloc();
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if (!priv->desc) {
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free(priv);
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return -ENOMEM;
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}
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ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
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if (ret)
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return ret;
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priv->mmc_is_wp = wp;
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priv->mmc_cd = cd;
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priv->id = id;
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priv->regs = mxs_ssp_regs_by_bus(id);
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priv->cfg.name = "MXS MMC";
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priv->cfg.ops = &mxsmmc_ops;
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priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
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priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
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MMC_MODE_HS_52MHz | MMC_MODE_HS;
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/*
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* SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
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* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
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* CLOCK_DIVIDE has to be an even value from 2 to 254, and
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* CLOCK_RATE could be any integer from 0 to 255.
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*/
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priv->cfg.f_min = 400000;
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priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id)
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* 1000 / 2;
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priv->cfg.b_max = 0x20;
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mmc = mmc_create(&priv->cfg, priv);
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if (!mmc) {
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mxs_dma_desc_free(priv->desc);
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free(priv);
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return -ENOMEM;
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}
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return 0;
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}
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#endif /* CONFIG_IS_ENABLED(DM_MMC) */
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2012-07-06 21:25:55 +00:00
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static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
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{
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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uint32_t *data_ptr;
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int timeout = MXSMMC_MAX_TIMEOUT;
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uint32_t reg;
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uint32_t data_count = data->blocksize * data->blocks;
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if (data->flags & MMC_DATA_READ) {
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data_ptr = (uint32_t *)data->dest;
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while (data_count && --timeout) {
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reg = readl(&ssp_regs->hw_ssp_status);
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if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
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*data_ptr++ = readl(&ssp_regs->hw_ssp_data);
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data_count -= 4;
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timeout = MXSMMC_MAX_TIMEOUT;
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} else
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udelay(1000);
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}
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} else {
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data_ptr = (uint32_t *)data->src;
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timeout *= 100;
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while (data_count && --timeout) {
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reg = readl(&ssp_regs->hw_ssp_status);
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if (!(reg & SSP_STATUS_FIFO_FULL)) {
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writel(*data_ptr++, &ssp_regs->hw_ssp_data);
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data_count -= 4;
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timeout = MXSMMC_MAX_TIMEOUT;
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} else
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udelay(1000);
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}
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}
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2016-07-19 07:33:36 +00:00
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return timeout ? 0 : -ECOMM;
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2012-07-06 21:25:55 +00:00
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}
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2012-07-06 21:25:56 +00:00
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2012-07-06 21:25:55 +00:00
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static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
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{
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uint32_t data_count = data->blocksize * data->blocks;
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int dmach;
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2012-07-06 21:25:57 +00:00
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struct mxs_dma_desc *desc = priv->desc;
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2012-11-06 11:27:29 +00:00
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void *addr;
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unsigned int flags;
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struct bounce_buffer bbstate;
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2012-07-06 21:25:57 +00:00
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memset(desc, 0, sizeof(struct mxs_dma_desc));
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desc->address = (dma_addr_t)desc;
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2012-07-06 21:25:55 +00:00
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if (data->flags & MMC_DATA_READ) {
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priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
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2012-08-26 15:19:07 +00:00
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addr = data->dest;
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flags = GEN_BB_WRITE;
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2012-07-06 21:25:55 +00:00
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} else {
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priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
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2012-08-26 15:19:07 +00:00
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addr = (void *)data->src;
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flags = GEN_BB_READ;
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}
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2012-11-06 11:27:29 +00:00
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bounce_buffer_start(&bbstate, addr, data_count, flags);
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2012-08-26 15:19:07 +00:00
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2012-11-06 11:27:29 +00:00
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priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
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2012-08-31 16:18:10 +00:00
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2012-07-06 21:25:55 +00:00
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priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
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(data_count << MXS_DMA_DESC_BYTES_OFFSET);
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2019-09-05 07:54:59 +00:00
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#if !CONFIG_IS_ENABLED(DM_MMC)
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mxs: mmc: spi: dma: Better wrap the MXS differences
This patch streamlines the differences between the MX23 and MX28 by
implementing a few helper functions to handle different DMA channel
mapping, different clock domain for SSP block and fixes a few minor
bugs.
First of all, the DMA channel mapping is now fixed in dma.h by defining
the actual channel map for both MX23 and MX28. Thus, MX23 now does no
longer use MX28 channel map which was wrong. Also, there is a fix for
MX28 DMA channel map, where the last four channels were incorrect.
Next, because correct DMA channel map is in place, the mxs_dma_init_channel()
call now bases the channel ID starting from SSP port #0. This removes the
need for DMA channel offset being added and cleans up the code. For the
same reason, the SSP0 offset can now be used in mxs_dma_desc_append(), thus
no need to adjust dma channel number in the driver either.
Lastly, the SSP clock ID is now retrieved by calling mxs_ssp_clock_by_bus()
which handles the fact that MX23 has shared SSP clock for both ports, while
MX28 has per-port SSP clock.
Finally, the mxs_ssp_bus_id_valid() pulls out two implementations of the
same functionality from MMC and SPI driver into common code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-02-23 02:42:58 +00:00
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dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
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2019-09-05 07:54:59 +00:00
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#else
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dmach = priv->dma_channel;
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#endif
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2012-07-06 21:25:55 +00:00
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mxs_dma_desc_append(dmach, priv->desc);
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2012-08-26 15:19:07 +00:00
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if (mxs_dma_go(dmach)) {
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2012-11-06 11:27:29 +00:00
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bounce_buffer_stop(&bbstate);
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2016-07-19 07:33:36 +00:00
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return -ECOMM;
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2012-08-26 15:19:07 +00:00
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}
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2012-07-06 21:25:55 +00:00
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2012-11-06 11:27:29 +00:00
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bounce_buffer_stop(&bbstate);
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2012-08-26 15:19:07 +00:00
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2012-07-06 21:25:55 +00:00
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return 0;
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}
|
|
|
|
|
2019-09-05 07:54:59 +00:00
|
|
|
#if !CONFIG_IS_ENABLED(DM_MMC)
|
2011-11-08 23:18:09 +00:00
|
|
|
/*
|
|
|
|
* Sends a command out on the bus. Takes the mmc pointer,
|
|
|
|
* a command pointer, and an optional data pointer.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
|
|
|
|
{
|
2014-03-11 17:34:20 +00:00
|
|
|
struct mxsmmc_priv *priv = mmc->priv;
|
2012-08-05 09:05:31 +00:00
|
|
|
struct mxs_ssp_regs *ssp_regs = priv->regs;
|
2019-09-05 07:54:59 +00:00
|
|
|
#else
|
|
|
|
static int
|
|
|
|
mxsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
|
|
|
|
{
|
|
|
|
struct mxsmmc_platdata *plat = dev_get_platdata(dev);
|
|
|
|
struct mxsmmc_priv *priv = dev_get_priv(dev);
|
|
|
|
struct mxs_ssp_regs *ssp_regs = priv->regs;
|
|
|
|
struct mmc *mmc = &plat->mmc;
|
|
|
|
#endif
|
2011-11-08 23:18:09 +00:00
|
|
|
uint32_t reg;
|
|
|
|
int timeout;
|
|
|
|
uint32_t ctrl0;
|
2012-07-06 21:25:55 +00:00
|
|
|
int ret;
|
2019-09-05 07:54:59 +00:00
|
|
|
#if !CONFIG_IS_ENABLED(DM_MMC)
|
|
|
|
int devnum = mmc->block_dev.devnum;
|
|
|
|
#else
|
|
|
|
int devnum = mmc_get_blk_desc(mmc)->devnum;
|
|
|
|
#endif
|
|
|
|
debug("MMC%d: CMD%d\n", devnum, cmd->cmdidx);
|
2011-11-08 23:18:09 +00:00
|
|
|
|
|
|
|
/* Check bus busy */
|
|
|
|
timeout = MXSMMC_MAX_TIMEOUT;
|
|
|
|
while (--timeout) {
|
|
|
|
udelay(1000);
|
|
|
|
reg = readl(&ssp_regs->hw_ssp_status);
|
|
|
|
if (!(reg &
|
|
|
|
(SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
|
|
|
|
SSP_STATUS_CMD_BUSY))) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!timeout) {
|
2019-09-05 07:54:59 +00:00
|
|
|
printf("MMC%d: Bus busy timeout!\n", devnum);
|
2016-07-19 07:33:36 +00:00
|
|
|
return -ETIMEDOUT;
|
2011-11-08 23:18:09 +00:00
|
|
|
}
|
2019-09-05 07:54:59 +00:00
|
|
|
#if !CONFIG_IS_ENABLED(DM_MMC)
|
2011-11-08 23:18:09 +00:00
|
|
|
/* See if card is present */
|
2013-01-22 15:01:03 +00:00
|
|
|
if (!mxsmmc_cd(priv)) {
|
2019-09-05 07:54:59 +00:00
|
|
|
printf("MMC%d: No card detected!\n", devnum);
|
2016-07-19 07:33:36 +00:00
|
|
|
return -ENOMEDIUM;
|
2011-11-08 23:18:09 +00:00
|
|
|
}
|
2019-09-05 07:54:59 +00:00
|
|
|
#endif
|
2011-11-08 23:18:09 +00:00
|
|
|
/* Start building CTRL0 contents */
|
|
|
|
ctrl0 = priv->buswidth;
|
|
|
|
|
|
|
|
/* Set up command */
|
|
|
|
if (!(cmd->resp_type & MMC_RSP_CRC))
|
|
|
|
ctrl0 |= SSP_CTRL0_IGNORE_CRC;
|
|
|
|
if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
|
|
|
|
ctrl0 |= SSP_CTRL0_GET_RESP;
|
|
|
|
if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
|
|
|
|
ctrl0 |= SSP_CTRL0_LONG_RESP;
|
|
|
|
|
2012-07-06 21:25:57 +00:00
|
|
|
if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
|
|
|
|
writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
|
|
|
|
else
|
|
|
|
writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
|
|
|
|
|
2011-11-08 23:18:09 +00:00
|
|
|
/* Command index */
|
|
|
|
reg = readl(&ssp_regs->hw_ssp_cmd0);
|
|
|
|
reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
|
|
|
|
reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
|
|
|
|
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
|
|
|
|
reg |= SSP_CMD0_APPEND_8CYC;
|
|
|
|
writel(reg, &ssp_regs->hw_ssp_cmd0);
|
|
|
|
|
|
|
|
/* Command argument */
|
|
|
|
writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
|
|
|
|
|
|
|
|
/* Set up data */
|
|
|
|
if (data) {
|
|
|
|
/* READ or WRITE */
|
|
|
|
if (data->flags & MMC_DATA_READ) {
|
|
|
|
ctrl0 |= SSP_CTRL0_READ;
|
2019-09-05 07:54:59 +00:00
|
|
|
#if !CONFIG_IS_ENABLED(DM_MMC)
|
2012-05-01 11:09:52 +00:00
|
|
|
} else if (priv->mmc_is_wp &&
|
2019-09-05 07:54:59 +00:00
|
|
|
priv->mmc_is_wp(devnum)) {
|
|
|
|
printf("MMC%d: Can not write a locked card!\n", devnum);
|
2016-07-19 07:33:36 +00:00
|
|
|
return -EOPNOTSUPP;
|
2019-09-05 07:54:59 +00:00
|
|
|
#endif
|
2011-11-08 23:18:09 +00:00
|
|
|
}
|
|
|
|
ctrl0 |= SSP_CTRL0_DATA_XFER;
|
2013-01-22 15:01:04 +00:00
|
|
|
|
|
|
|
reg = data->blocksize * data->blocks;
|
|
|
|
#if defined(CONFIG_MX23)
|
|
|
|
ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
|
|
|
|
|
|
|
|
clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
|
|
|
|
SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
|
|
|
|
((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
|
|
|
|
((ffs(data->blocksize) - 1) <<
|
|
|
|
SSP_CMD0_BLOCK_SIZE_OFFSET));
|
|
|
|
#elif defined(CONFIG_MX28)
|
|
|
|
writel(reg, &ssp_regs->hw_ssp_xfer_size);
|
|
|
|
|
2011-11-08 23:18:09 +00:00
|
|
|
reg = ((data->blocks - 1) <<
|
|
|
|
SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
|
|
|
|
((ffs(data->blocksize) - 1) <<
|
|
|
|
SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
|
|
|
|
writel(reg, &ssp_regs->hw_ssp_block_size);
|
2013-01-22 15:01:04 +00:00
|
|
|
#endif
|
2011-11-08 23:18:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Kick off the command */
|
|
|
|
ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
|
|
|
|
writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
|
|
|
|
|
|
|
|
/* Wait for the command to complete */
|
|
|
|
timeout = MXSMMC_MAX_TIMEOUT;
|
|
|
|
while (--timeout) {
|
|
|
|
udelay(1000);
|
|
|
|
reg = readl(&ssp_regs->hw_ssp_status);
|
|
|
|
if (!(reg & SSP_STATUS_CMD_BUSY))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!timeout) {
|
2019-09-05 07:54:59 +00:00
|
|
|
printf("MMC%d: Command %d busy\n", devnum, cmd->cmdidx);
|
2016-07-19 07:33:36 +00:00
|
|
|
return -ETIMEDOUT;
|
2011-11-08 23:18:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Check command timeout */
|
|
|
|
if (reg & SSP_STATUS_RESP_TIMEOUT) {
|
2019-09-05 07:55:00 +00:00
|
|
|
debug("MMC%d: Command %d timeout (status 0x%08x)\n",
|
|
|
|
devnum, cmd->cmdidx, reg);
|
2016-07-19 07:33:36 +00:00
|
|
|
return -ETIMEDOUT;
|
2011-11-08 23:18:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Check command errors */
|
|
|
|
if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
|
|
|
|
printf("MMC%d: Command %d error (status 0x%08x)!\n",
|
2019-09-05 07:54:59 +00:00
|
|
|
devnum, cmd->cmdidx, reg);
|
2016-07-19 07:33:36 +00:00
|
|
|
return -ECOMM;
|
2011-11-08 23:18:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Copy response to response buffer */
|
|
|
|
if (cmd->resp_type & MMC_RSP_136) {
|
|
|
|
cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
|
|
|
|
cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
|
|
|
|
cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
|
|
|
|
cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
|
|
|
|
} else
|
|
|
|
cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
|
|
|
|
|
|
|
|
/* Return if no data to process */
|
|
|
|
if (!data)
|
|
|
|
return 0;
|
|
|
|
|
2012-07-06 21:25:56 +00:00
|
|
|
if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
|
|
|
|
ret = mxsmmc_send_cmd_pio(priv, data);
|
|
|
|
if (ret) {
|
|
|
|
printf("MMC%d: Data timeout with command %d "
|
2019-09-05 07:54:59 +00:00
|
|
|
"(status 0x%08x)!\n", devnum, cmd->cmdidx, reg);
|
2012-07-06 21:25:56 +00:00
|
|
|
return ret;
|
|
|
|
}
|
2012-07-06 21:25:57 +00:00
|
|
|
} else {
|
|
|
|
ret = mxsmmc_send_cmd_dma(priv, data);
|
|
|
|
if (ret) {
|
2019-09-05 07:54:59 +00:00
|
|
|
printf("MMC%d: DMA transfer failed\n", devnum);
|
2012-07-06 21:25:57 +00:00
|
|
|
return ret;
|
|
|
|
}
|
2012-04-05 03:30:35 +00:00
|
|
|
}
|
2012-03-15 18:33:21 +00:00
|
|
|
|
2011-11-08 23:18:09 +00:00
|
|
|
/* Check data errors */
|
|
|
|
reg = readl(&ssp_regs->hw_ssp_status);
|
|
|
|
if (reg &
|
|
|
|
(SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
|
|
|
|
SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
|
|
|
|
printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
|
2019-09-05 07:54:59 +00:00
|
|
|
devnum, cmd->cmdidx, reg);
|
2016-07-19 07:33:36 +00:00
|
|
|
return -ECOMM;
|
2011-11-08 23:18:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-09-05 07:54:59 +00:00
|
|
|
#if CONFIG_IS_ENABLED(DM_MMC)
|
|
|
|
/* Base numbers of i.MX2[38] clk for ssp0 IP block */
|
|
|
|
#define MXS_SSP_IMX23_CLKID_SSP0 33
|
|
|
|
#define MXS_SSP_IMX28_CLKID_SSP0 46
|
|
|
|
|
|
|
|
static int mxsmmc_get_cd(struct udevice *dev)
|
2011-11-08 23:18:09 +00:00
|
|
|
{
|
2019-09-05 07:54:59 +00:00
|
|
|
struct mxsmmc_platdata *plat = dev_get_platdata(dev);
|
|
|
|
struct mxsmmc_priv *priv = dev_get_priv(dev);
|
|
|
|
struct mxs_ssp_regs *ssp_regs = priv->regs;
|
|
|
|
|
|
|
|
if (plat->non_removable)
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mxsmmc_set_ios(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct mxsmmc_platdata *plat = dev_get_platdata(dev);
|
|
|
|
struct mxsmmc_priv *priv = dev_get_priv(dev);
|
2012-08-05 09:05:31 +00:00
|
|
|
struct mxs_ssp_regs *ssp_regs = priv->regs;
|
2019-09-05 07:54:59 +00:00
|
|
|
struct mmc *mmc = &plat->mmc;
|
2011-11-08 23:18:09 +00:00
|
|
|
|
|
|
|
/* Set the clock speed */
|
|
|
|
if (mmc->clock)
|
2019-09-05 07:54:59 +00:00
|
|
|
mxs_set_ssp_busclock(priv->clkid, mmc->clock / 1000);
|
2011-11-08 23:18:09 +00:00
|
|
|
|
|
|
|
switch (mmc->bus_width) {
|
|
|
|
case 1:
|
|
|
|
priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set the bus width */
|
|
|
|
clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
|
|
|
|
SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
|
|
|
|
|
2019-09-05 07:54:59 +00:00
|
|
|
debug("MMC%d: Set %d bits bus width\n", mmc_get_blk_desc(mmc)->devnum,
|
|
|
|
mmc->bus_width);
|
2016-12-30 06:30:16 +00:00
|
|
|
|
|
|
|
return 0;
|
2011-11-08 23:18:09 +00:00
|
|
|
}
|
|
|
|
|
2019-09-05 07:54:59 +00:00
|
|
|
static int mxsmmc_init(struct udevice *dev)
|
2011-11-08 23:18:09 +00:00
|
|
|
{
|
2019-09-05 07:54:59 +00:00
|
|
|
struct mxsmmc_priv *priv = dev_get_priv(dev);
|
2012-08-05 09:05:31 +00:00
|
|
|
struct mxs_ssp_regs *ssp_regs = priv->regs;
|
2011-11-08 23:18:09 +00:00
|
|
|
|
|
|
|
/* Reset SSP */
|
2012-08-13 09:53:12 +00:00
|
|
|
mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
|
2011-11-08 23:18:09 +00:00
|
|
|
|
2013-01-22 15:01:02 +00:00
|
|
|
/* Reconfigure the SSP block for MMC operation */
|
|
|
|
writel(SSP_CTRL1_SSP_MODE_SD_MMC |
|
|
|
|
SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
|
|
|
|
SSP_CTRL1_DMA_ENABLE |
|
|
|
|
SSP_CTRL1_POLARITY |
|
|
|
|
SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
|
|
|
|
SSP_CTRL1_DATA_CRC_IRQ_EN |
|
|
|
|
SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
|
|
|
|
SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
|
|
|
|
SSP_CTRL1_RESP_ERR_IRQ_EN,
|
|
|
|
&ssp_regs->hw_ssp_ctrl1_set);
|
2011-11-08 23:18:09 +00:00
|
|
|
|
|
|
|
/* Set initial bit clock 400 KHz */
|
2019-09-05 07:54:59 +00:00
|
|
|
mxs_set_ssp_busclock(priv->clkid, 400);
|
2011-11-08 23:18:09 +00:00
|
|
|
|
|
|
|
/* Send initial 74 clock cycles (185 us @ 400 KHz)*/
|
|
|
|
writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
|
|
|
|
udelay(200);
|
|
|
|
writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-09-05 07:54:59 +00:00
|
|
|
static int mxsmmc_probe(struct udevice *dev)
|
2011-11-08 23:18:09 +00:00
|
|
|
{
|
2019-09-05 07:54:59 +00:00
|
|
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
|
|
|
struct mxsmmc_platdata *plat = dev_get_platdata(dev);
|
|
|
|
struct mxsmmc_priv *priv = dev_get_priv(dev);
|
|
|
|
struct blk_desc *bdesc;
|
|
|
|
struct mmc *mmc;
|
|
|
|
int ret, clkid;
|
|
|
|
|
|
|
|
debug("%s: probe\n", __func__);
|
|
|
|
|
|
|
|
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
|
|
struct dtd_fsl_imx_mmc *dtplat = &plat->dtplat;
|
|
|
|
struct phandle_1_arg *p1a = &dtplat->clocks[0];
|
|
|
|
|
|
|
|
priv->buswidth = dtplat->bus_width;
|
|
|
|
priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0];
|
|
|
|
priv->dma_channel = dtplat->dmas[1];
|
|
|
|
clkid = p1a->arg[0];
|
|
|
|
plat->non_removable = dtplat->non_removable;
|
|
|
|
|
|
|
|
debug("OF_PLATDATA: regs: 0x%p bw: %d clkid: %d non_removable: %d\n",
|
|
|
|
priv->regs, priv->buswidth, clkid, plat->non_removable);
|
|
|
|
#else
|
|
|
|
priv->regs = (struct mxs_ssp_regs *)plat->base;
|
|
|
|
priv->dma_channel = plat->dma_id;
|
|
|
|
clkid = plat->clk_id;
|
|
|
|
#endif
|
2011-11-08 23:18:09 +00:00
|
|
|
|
2019-09-05 07:54:59 +00:00
|
|
|
#ifdef CONFIG_MX28
|
|
|
|
priv->clkid = clkid - MXS_SSP_IMX28_CLKID_SSP0;
|
|
|
|
#else /* CONFIG_MX23 */
|
|
|
|
priv->clkid = clkid - MXS_SSP_IMX23_CLKID_SSP0;
|
|
|
|
#endif
|
|
|
|
mmc = &plat->mmc;
|
|
|
|
mmc->cfg = &plat->cfg;
|
|
|
|
mmc->dev = dev;
|
2011-11-08 23:18:09 +00:00
|
|
|
|
2012-03-15 18:33:21 +00:00
|
|
|
priv->desc = mxs_dma_desc_alloc();
|
|
|
|
if (!priv->desc) {
|
2019-09-05 07:54:59 +00:00
|
|
|
printf("%s: Cannot allocate DMA descriptor\n", __func__);
|
2012-03-15 18:33:21 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2019-09-05 07:54:59 +00:00
|
|
|
ret = mxs_dma_init_channel(priv->dma_channel);
|
2012-04-08 17:34:46 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2019-09-05 07:54:59 +00:00
|
|
|
plat->cfg.name = "MXS MMC";
|
|
|
|
plat->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
2011-11-08 23:18:09 +00:00
|
|
|
|
2019-09-05 07:54:59 +00:00
|
|
|
plat->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
|
|
|
|
MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
2011-11-08 23:18:09 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
|
|
|
|
* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
|
|
|
|
* CLOCK_DIVIDE has to be an even value from 2 to 254, and
|
|
|
|
* CLOCK_RATE could be any integer from 0 to 255.
|
|
|
|
*/
|
2019-09-05 07:54:59 +00:00
|
|
|
plat->cfg.f_min = 400000;
|
|
|
|
plat->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + priv->clkid) * 1000 / 2;
|
|
|
|
plat->cfg.b_max = 0x20;
|
2011-11-08 23:18:09 +00:00
|
|
|
|
2019-09-05 07:54:59 +00:00
|
|
|
bdesc = mmc_get_blk_desc(mmc);
|
|
|
|
if (!bdesc) {
|
|
|
|
printf("%s: No block device descriptor!\n", __func__);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (plat->non_removable)
|
|
|
|
bdesc->removable = 0;
|
|
|
|
|
|
|
|
ret = mxsmmc_init(dev);
|
|
|
|
if (ret)
|
|
|
|
printf("%s: MMC%d init error %d\n", __func__,
|
|
|
|
bdesc->devnum, ret);
|
|
|
|
|
|
|
|
/* Set the initial clock speed */
|
|
|
|
mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
|
|
|
|
|
|
|
|
upriv->mmc = mmc;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
};
|
|
|
|
|
|
|
|
#if CONFIG_IS_ENABLED(BLK)
|
|
|
|
static int mxsmmc_bind(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct mxsmmc_platdata *plat = dev_get_platdata(dev);
|
|
|
|
|
|
|
|
return mmc_bind(dev, &plat->mmc, &plat->cfg);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static const struct dm_mmc_ops mxsmmc_ops = {
|
|
|
|
.get_cd = mxsmmc_get_cd,
|
|
|
|
.send_cmd = mxsmmc_send_cmd,
|
|
|
|
.set_ios = mxsmmc_set_ios,
|
|
|
|
};
|
|
|
|
|
|
|
|
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
|
|
static int mxsmmc_ofdata_to_platdata(struct udevice *bus)
|
|
|
|
{
|
|
|
|
struct mxsmmc_platdata *plat = bus->platdata;
|
|
|
|
u32 prop[2];
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
plat->base = dev_read_addr(bus);
|
|
|
|
plat->buswidth =
|
|
|
|
dev_read_u32_default(bus, "bus-width", 1);
|
|
|
|
plat->non_removable = dev_read_bool(bus, "non-removable");
|
|
|
|
|
|
|
|
ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
|
|
|
|
if (ret) {
|
|
|
|
printf("%s: Reading 'dmas' property failed!\n", __func__);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
plat->dma_id = prop[1];
|
|
|
|
|
|
|
|
ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
|
|
|
|
if (ret) {
|
|
|
|
printf("%s: Reading 'clocks' property failed!\n", __func__);
|
|
|
|
return ret;
|
2014-03-11 17:34:20 +00:00
|
|
|
}
|
2019-09-05 07:54:59 +00:00
|
|
|
plat->clk_id = prop[1];
|
|
|
|
|
|
|
|
debug("%s: base=0x%x, bus_width=%d %s dma_id=%d clk_id=%d\n",
|
|
|
|
__func__, (uint)plat->base, plat->buswidth,
|
|
|
|
plat->non_removable ? "non-removable" : NULL,
|
|
|
|
plat->dma_id, plat->clk_id);
|
|
|
|
|
2011-11-08 23:18:09 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2019-09-05 07:54:59 +00:00
|
|
|
|
|
|
|
static const struct udevice_id mxsmmc_ids[] = {
|
|
|
|
{ .compatible = "fsl,imx23-mmc", },
|
|
|
|
{ .compatible = "fsl,imx28-mmc", },
|
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2020-06-25 04:10:04 +00:00
|
|
|
U_BOOT_DRIVER(fsl_imx23_mmc) = {
|
2019-09-05 07:54:59 +00:00
|
|
|
.name = "fsl_imx23_mmc",
|
|
|
|
.id = UCLASS_MMC,
|
|
|
|
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
|
|
.of_match = mxsmmc_ids,
|
|
|
|
.ofdata_to_platdata = mxsmmc_ofdata_to_platdata,
|
|
|
|
#endif
|
|
|
|
.ops = &mxsmmc_ops,
|
|
|
|
#if CONFIG_IS_ENABLED(BLK)
|
|
|
|
.bind = mxsmmc_bind,
|
|
|
|
#endif
|
|
|
|
.probe = mxsmmc_probe,
|
|
|
|
.priv_auto_alloc_size = sizeof(struct mxsmmc_priv),
|
|
|
|
.platdata_auto_alloc_size = sizeof(struct mxsmmc_platdata),
|
|
|
|
};
|
|
|
|
|
2020-06-25 04:10:06 +00:00
|
|
|
U_BOOT_DRIVER_ALIAS(fsl_imx23_mmc, fsl_imx28_mmc)
|
2019-09-05 07:54:59 +00:00
|
|
|
#endif /* CONFIG_DM_MMC */
|