mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-23 08:01:59 +00:00
252 lines
5.7 KiB
Text
252 lines
5.7 KiB
Text
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// SPDX-License-Identifier: GPL-2.0+
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#include <stm32f7-u-boot.dtsi>
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/{
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chosen {
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bootargs = "root=/dev/ram rdinit=/linuxrc";
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};
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aliases {
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/* Aliases for gpios so as to use sequence */
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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mmc0 = &sdio;
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spi0 = &qspi;
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};
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backlight: backlight {
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compatible = "gpio-backlight";
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gpios = <&gpiok 3 0>;
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status = "okay";
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};
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button1 {
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compatible = "st,button1";
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button-gpio = <&gpioi 11 0>;
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};
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led1 {
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compatible = "st,led1";
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led-gpio = <&gpioi 1 0>;
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};
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panel-rgb@0 {
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compatible = "simple-panel";
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backlight = <&backlight>;
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enable-gpios = <&gpioi 12 0>;
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status = "okay";
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display-timings {
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timing@0 {
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clock-frequency = <9000000>;
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hactive = <480>;
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vactive = <272>;
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hfront-porch = <2>;
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hback-porch = <2>;
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hsync-len = <41>;
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vfront-porch = <2>;
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vback-porch = <2>;
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vsync-len = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <1>;
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};
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};
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};
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soc {
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ltdc: display-controller@40016800 {
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compatible = "st,stm32-ltdc";
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reg = <0x40016800 0x200>;
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resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
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pinctrl-0 = <<dc_pins>;
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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};
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};
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&clk_hse {
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u-boot,dm-pre-reloc;
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};
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&fmc {
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/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
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bank1: bank@0 {
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u-boot,dm-pre-reloc;
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st,sdram-control = /bits/ 8 <NO_COL_8
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NO_ROW_12
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MWIDTH_16
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BANKS_4
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CAS_3
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SDCLK_2
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RD_BURST_EN
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RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_2
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TXSR_6
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TRAS_4
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TRC_6
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TWR_2
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TRP_2
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TRCD_2>;
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/* refcount = (64msec/total_row_sdram)*freq - 20 */
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st,sdram-refcount = < 1542 >;
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};
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};
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&pinctrl {
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ethernet_mii: mii@0 {
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pins {
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pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
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<STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
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<STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
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<STM32F746_PA2_FUNC_ETH_MDIO>,
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<STM32F746_PC1_FUNC_ETH_MDC>,
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<STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
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<STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
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<STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
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<STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
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slew-rate = <2>;
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};
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};
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fmc_pins: fmc@0 {
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u-boot,dm-pre-reloc;
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pins {
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u-boot,dm-pre-reloc;
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pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
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<STM32F746_PD9_FUNC_FMC_D14>,
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<STM32F746_PD8_FUNC_FMC_D13>,
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<STM32F746_PE15_FUNC_FMC_D12>,
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<STM32F746_PE14_FUNC_FMC_D11>,
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<STM32F746_PE13_FUNC_FMC_D10>,
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<STM32F746_PE12_FUNC_FMC_D9>,
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<STM32F746_PE11_FUNC_FMC_D8>,
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<STM32F746_PE10_FUNC_FMC_D7>,
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<STM32F746_PE9_FUNC_FMC_D6>,
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<STM32F746_PE8_FUNC_FMC_D5>,
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<STM32F746_PE7_FUNC_FMC_D4>,
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<STM32F746_PD1_FUNC_FMC_D3>,
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<STM32F746_PD0_FUNC_FMC_D2>,
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<STM32F746_PD15_FUNC_FMC_D1>,
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<STM32F746_PD14_FUNC_FMC_D0>,
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<STM32F746_PE1_FUNC_FMC_NBL1>,
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<STM32F746_PE0_FUNC_FMC_NBL0>,
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<STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
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<STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
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<STM32F746_PG1_FUNC_FMC_A11>,
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<STM32F746_PG0_FUNC_FMC_A10>,
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<STM32F746_PF15_FUNC_FMC_A9>,
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<STM32F746_PF14_FUNC_FMC_A8>,
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<STM32F746_PF13_FUNC_FMC_A7>,
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<STM32F746_PF12_FUNC_FMC_A6>,
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<STM32F746_PF5_FUNC_FMC_A5>,
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<STM32F746_PF4_FUNC_FMC_A4>,
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<STM32F746_PF3_FUNC_FMC_A3>,
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<STM32F746_PF2_FUNC_FMC_A2>,
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<STM32F746_PF1_FUNC_FMC_A1>,
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<STM32F746_PF0_FUNC_FMC_A0>,
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<STM32F746_PH3_FUNC_FMC_SDNE0>,
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<STM32F746_PH5_FUNC_FMC_SDNWE>,
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<STM32F746_PF11_FUNC_FMC_SDNRAS>,
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<STM32F746_PG15_FUNC_FMC_SDNCAS>,
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<STM32F746_PC3_FUNC_FMC_SDCKE0>,
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<STM32F746_PG8_FUNC_FMC_SDCLK>;
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slew-rate = <2>;
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};
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};
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ltdc_pins: ltdc@0 {
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pins {
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pinmux = <STM32F746_PE4_FUNC_LCD_B0>,
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<STM32F746_PG12_FUNC_LCD_B4>,
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<STM32F746_PI9_FUNC_LCD_VSYNC>,
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<STM32F746_PI10_FUNC_LCD_HSYNC>,
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<STM32F746_PI14_FUNC_LCD_CLK>,
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<STM32F746_PI15_FUNC_LCD_R0>,
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<STM32F746_PJ0_FUNC_LCD_R1>,
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<STM32F746_PJ1_FUNC_LCD_R2>,
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<STM32F746_PJ2_FUNC_LCD_R3>,
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<STM32F746_PJ3_FUNC_LCD_R4>,
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<STM32F746_PJ4_FUNC_LCD_R5>,
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<STM32F746_PJ5_FUNC_LCD_R6>,
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<STM32F746_PJ6_FUNC_LCD_R7>,
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<STM32F746_PJ7_FUNC_LCD_G0>,
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<STM32F746_PJ8_FUNC_LCD_G1>,
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<STM32F746_PJ9_FUNC_LCD_G2>,
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<STM32F746_PJ10_FUNC_LCD_G3>,
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<STM32F746_PJ11_FUNC_LCD_G4>,
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<STM32F746_PJ13_FUNC_LCD_B1>,
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<STM32F746_PJ14_FUNC_LCD_B2>,
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<STM32F746_PJ15_FUNC_LCD_B3>,
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<STM32F746_PK0_FUNC_LCD_G5>,
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<STM32F746_PK1_FUNC_LCD_G6>,
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<STM32F746_PK2_FUNC_LCD_G7>,
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<STM32F746_PK4_FUNC_LCD_B5>,
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<STM32F746_PK5_FUNC_LCD_B6>,
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<STM32F746_PK6_FUNC_LCD_B7>,
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<STM32F746_PK7_FUNC_LCD_DE>;
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slew-rate = <2>;
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};
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};
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qspi_pins: qspi@0 {
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pins {
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pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
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<STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
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<STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
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<STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
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<STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
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<STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
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slew-rate = <2>;
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};
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};
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usart1_pins_a: usart1@0 {
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u-boot,dm-pre-reloc;
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pins1 {
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u-boot,dm-pre-reloc;
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};
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pins2 {
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u-boot,dm-pre-reloc;
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};
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};
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};
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&pwrcfg {
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u-boot,dm-pre-reloc;
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};
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&qspi {
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qflash0: n25q128a {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q128a13", "jedec,spi-nor";
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spi-max-frequency = <108000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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memory-map = <0x90000000 0x1000000>;
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reg = <0>;
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};
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};
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&timer5 {
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u-boot,dm-pre-reloc;
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};
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