Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2025-03-02 14:27:17 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/arch/arm/mach-socfpga/Kconfig

151 lines
4 KiB
Text
Raw Normal View History

ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 20:38:20 +09:00
if ARCH_SOCFPGA
Convert CONFIG_SPL_LIBCOMMON_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-12 23:18:41 -06:00
config SPL_LIBCOMMON_SUPPORT
default y
Convert CONFIG_SPL_LIBDISK_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-12 23:18:42 -06:00
config SPL_LIBDISK_SUPPORT
default y
Convert CONFIG_SPL_LIBGENERIC_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-12 23:18:43 -06:00
config SPL_LIBGENERIC_SUPPORT
default y
Convert CONFIG_SPL_MMC_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-12 23:18:44 -06:00
config SPL_MMC_SUPPORT
default y if DM_MMC
Convert CONFIG_SPL_NAND_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-12 23:18:48 -06:00
config SPL_NAND_SUPPORT
default y if SPL_NAND_DENALI
Convert CONFIG_SPL_SERIAL_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-12 23:18:56 -06:00
config SPL_SERIAL_SUPPORT
default y
Convert CONFIG_SPL_SPI_FLASH_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-12 23:18:57 -06:00
config SPL_SPI_FLASH_SUPPORT
Convert CONFIG_SPL_SPI_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-12 23:18:58 -06:00
default y if SPL_SPI_SUPPORT
config SPL_SPI_SUPPORT
Convert CONFIG_SPL_SPI_FLASH_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-12 23:18:57 -06:00
default y if DM_SPI
Convert CONFIG_SPL_WATCHDOG_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-12 23:19:02 -06:00
config SPL_WATCHDOG_SUPPORT
default y
SPL: add support to boot from a partition type the socfpga bootrom supports mmc booting from either a raw image starting at 0x0, or from a partition of type 0xa2. This patch adds support for locating the boot image in the first type 0xa2 partition found. Assigned a partition number of -1 will cause a search for a partition of type CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE and use it to find the u-boot image Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2017-02-10 17:15:34 -08:00
config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
default y
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
default 0xa2
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 21:57:57 +02:00
config TARGET_SOCFPGA_ARRIA5
bool
arm: socfpga: introduce TARGET_SOCFPGA_GEN5 config property In order to re-use as much Cyclone5 and Arria5 code as possible to support the Arria10 platform, we need to wrap some of the code with #ifdef's. By adding CONFIG_TARGET_SOCFPGA_GEN5, we can shorten the check by not having to check for both AV || AV. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-02 13:31:25 -06:00
select TARGET_SOCFPGA_GEN5
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 21:57:57 +02:00
arm: socfpga: Enable build for Arria 10 Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-26 02:44:48 +08:00
config TARGET_SOCFPGA_ARRIA10
bool
Convert CONFIG_SPL_BOARD_INIT to Kconfig This converts the following to Kconfig: CONFIG_SPL_BOARD_INIT Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> [trini: Update the Kconfig logic] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-03 17:13:32 +08:00
select SPL_BOARD_INIT if SPL
arm: socfpga: Enable build for Arria 10 Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-26 02:44:48 +08:00
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 21:57:57 +02:00
config TARGET_SOCFPGA_CYCLONE5
bool
arm: socfpga: introduce TARGET_SOCFPGA_GEN5 config property In order to re-use as much Cyclone5 and Arria5 code as possible to support the Arria10 platform, we need to wrap some of the code with #ifdef's. By adding CONFIG_TARGET_SOCFPGA_GEN5, we can shorten the check by not having to check for both AV || AV. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-02 13:31:25 -06:00
select TARGET_SOCFPGA_GEN5
config TARGET_SOCFPGA_GEN5
bool
arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig Convert Altera DDR SDRAM driver to use Kconfig method. Enable ALTERA_SDRAM by default if it is on Gen5 target. Arria 10 will have different driver. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-05 17:32:51 +08:00
select ALTERA_SDRAM
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 21:57:57 +02:00
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 20:38:20 +09:00
choice
prompt "Altera SOCFPGA board select"
arch: Make board selection choices optional By making the board selections optional, every defconfig will include the board selection when running savedefconfig so if a new board is added to the top of the list of choices the former top's defconfig will still be correct. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com>
2015-05-12 14:46:23 -05:00
optional
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 20:38:20 +09:00
arm: socfpga: Enable build for Arria 10 Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-26 02:44:48 +08:00
config TARGET_SOCFPGA_ARRIA10_SOCDK
bool "Altera SOCFPGA SoCDK (Arria 10)"
select TARGET_SOCFPGA_ARRIA10
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 21:57:57 +02:00
config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 20:38:20 +09:00
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 21:57:57 +02:00
config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 20:38:20 +09:00
ARM: socfpga: Rename MCVEVK The board is now manufactured by Aries Embedded GmbH , rename it. Signed-off-by: Marek Vasut <marex@denx.de>
2017-04-05 13:17:03 +02:00
config TARGET_SOCFPGA_ARIES_MCVEVK
bool "Aries MCVEVK (Cyclone V)"
arm: socfpga: Add support for DENX MCV SoM and MCVEVK board Add support for DENX MCV SoM, which is CycloneV based and the associated DENX MCVEVK baseboard. The board can boot from eMMC. Ethernet and USB is supported. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-03 01:37:28 +02:00
select TARGET_SOCFPGA_CYCLONE5
arm: socfpga: Repair SoCrates board This board was constantly parasiting on the CV SoCDK, so split it into it's own separate directory. Moreover, the board config was missing important bits, like simple-bus support in SPL, the DRAM configuration was incorrect and the DTS was also missing the pre reloc bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Jan Viktorin <viktorin@rehivetech.com>
2015-11-23 17:06:27 +01:00
config TARGET_SOCFPGA_EBV_SOCRATES
bool "EBV SoCrates (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
ARM: socfpga: add support for IS1 board This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA. Signed-off-by: Pavel Machek <pavel@denx.de>
2016-06-07 12:37:23 +02:00
config TARGET_SOCFPGA_IS1
bool "IS1 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
arm: socfpga: Add samtec VIN|ING board Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- V2: Update the defconfig as per Tom's request
2015-12-01 18:09:52 +01:00
config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
bool "samtec VIN|ING FPGA (Cyclone V)"
Kconfig: Migrate BOARD_LATE_INIT to a select This option should not really be user selectable. Note that on PowerPC we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be conditional on that. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
2017-01-22 19:43:11 -05:00
select BOARD_LATE_INIT
arm: socfpga: Add samtec VIN|ING board Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- V2: Update the defconfig as per Tom's request
2015-12-01 18:09:52 +01:00
select TARGET_SOCFPGA_CYCLONE5
ARM: socfpga: Sort Kconfig entries Just sort the board entries, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-06-08 02:57:05 +02:00
config TARGET_SOCFPGA_SR1500
bool "SR1500 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
arm: socfpga: Add support for the Terasic DE-0 Atlas board Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-01 17:41:52 -05:00
config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
arm: socfpga: add cyclone5 based de10-nano board Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-04-18 08:11:16 -07:00
config TARGET_SOCFPGA_TERASIC_DE10_NANO
bool "Terasic DE10-Nano (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
socfpga: add support for Terasic DE1-SoC board Add CycloneV based Terasic DE1-SoC board. The board boots from SD/MMC. Ethernet and USB host is supported. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
2016-11-14 16:07:10 +01:00
config TARGET_SOCFPGA_TERASIC_DE1_SOC
bool "Terasic DE1-SoC (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
arm: socfpga: Add support for Terasic SoCkit board Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut <marex@denx.de>
2015-06-21 17:28:53 +02:00
config TARGET_SOCFPGA_TERASIC_SOCKIT
bool "Terasic SoCkit (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 20:38:20 +09:00
endchoice
config SYS_BOARD
arm: socfpga: Split Altera socfpga into AV and CV SoCDK The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-10 21:24:53 +02:00
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
arm: socfpga: Enable build for Arria 10 Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-26 02:44:48 +08:00
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
arm: socfpga: Split Altera socfpga into AV and CV SoCDK The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-10 21:24:53 +02:00
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
arm: socfpga: Add support for the Terasic DE-0 Atlas board Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-01 17:41:52 -05:00
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
socfpga: add support for Terasic DE1-SoC board Add CycloneV based Terasic DE1-SoC board. The board boots from SD/MMC. Ethernet and USB host is supported. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
2016-11-14 16:07:10 +01:00
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
arm: socfpga: add cyclone5 based de10-nano board Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-04-18 08:11:16 -07:00
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
ARM: socfpga: add support for IS1 board This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA. Signed-off-by: Pavel Machek <pavel@denx.de>
2016-06-07 12:37:23 +02:00
default "is1" if TARGET_SOCFPGA_IS1
ARM: socfpga: Rename MCVEVK The board is now manufactured by Aries Embedded GmbH , rename it. Signed-off-by: Marek Vasut <marex@denx.de>
2017-04-05 13:17:03 +02:00
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
arm: socfpga: Add support for Terasic SoCkit board Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut <marex@denx.de>
2015-06-21 17:28:53 +02:00
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
arm: socfpga: Repair SoCrates board This board was constantly parasiting on the CV SoCDK, so split it into it's own separate directory. Moreover, the board config was missing important bits, like simple-bus support in SPL, the DRAM configuration was incorrect and the DTS was also missing the pre reloc bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Jan Viktorin <viktorin@rehivetech.com>
2015-11-23 17:06:27 +01:00
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
arm: socfpga: Add SoCFPGA SR1500 board The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices: - SPI NOR - eMMC - Ethernet Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
2015-11-18 11:06:09 +01:00
default "sr1500" if TARGET_SOCFPGA_SR1500
arm: socfpga: Add samtec VIN|ING board Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- V2: Update the defconfig as per Tom's request
2015-12-01 18:09:52 +01:00
default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 20:38:20 +09:00
config SYS_VENDOR
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 21:57:57 +02:00
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
arm: socfpga: Enable build for Arria 10 Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-26 02:44:48 +08:00
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 21:57:57 +02:00
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
ARM: socfpga: Rename MCVEVK The board is now manufactured by Aries Embedded GmbH , rename it. Signed-off-by: Marek Vasut <marex@denx.de>
2017-04-05 13:17:03 +02:00
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
arm: socfpga: Repair SoCrates board This board was constantly parasiting on the CV SoCDK, so split it into it's own separate directory. Moreover, the board config was missing important bits, like simple-bus support in SPL, the DRAM configuration was incorrect and the DTS was also missing the pre reloc bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Jan Viktorin <viktorin@rehivetech.com>
2015-11-23 17:06:27 +01:00
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
arm: socfpga: Add samtec VIN|ING board Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- V2: Update the defconfig as per Tom's request
2015-12-01 18:09:52 +01:00
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
arm: socfpga: Add support for the Terasic DE-0 Atlas board Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-01 17:41:52 -05:00
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
socfpga: add support for Terasic DE1-SoC board Add CycloneV based Terasic DE1-SoC board. The board boots from SD/MMC. Ethernet and USB host is supported. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
2016-11-14 16:07:10 +01:00
default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
arm: socfpga: add cyclone5 based de10-nano board Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-04-18 08:11:16 -07:00
default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
arm: socfpga: Add support for Terasic SoCkit board Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut <marex@denx.de>
2015-06-21 17:28:53 +02:00
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 20:38:20 +09:00
config SYS_SOC
default "socfpga"
config SYS_CONFIG_NAME
arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA board config files. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-22 17:01:32 -05:00
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
arm: socfpga: Enable build for Arria 10 Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-26 02:44:48 +08:00
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA board config files. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-22 17:01:32 -05:00
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
arm: socfpga: Add support for the Terasic DE-0 Atlas board Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-01 17:41:52 -05:00
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
socfpga: add support for Terasic DE1-SoC board Add CycloneV based Terasic DE1-SoC board. The board boots from SD/MMC. Ethernet and USB host is supported. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
2016-11-14 16:07:10 +01:00
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
arm: socfpga: add cyclone5 based de10-nano board Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-04-18 08:11:16 -07:00
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
ARM: socfpga: add support for IS1 board This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA. Signed-off-by: Pavel Machek <pavel@denx.de>
2016-06-07 12:37:23 +02:00
default "socfpga_is1" if TARGET_SOCFPGA_IS1
ARM: socfpga: Rename MCVEVK The board is now manufactured by Aries Embedded GmbH , rename it. Signed-off-by: Marek Vasut <marex@denx.de>
2017-04-05 13:17:03 +02:00
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
arm: socfpga: Add support for Terasic SoCkit board Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut <marex@denx.de>
2015-06-21 17:28:53 +02:00
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
arm: socfpga: Repair SoCrates board This board was constantly parasiting on the CV SoCDK, so split it into it's own separate directory. Moreover, the board config was missing important bits, like simple-bus support in SPL, the DRAM configuration was incorrect and the DTS was also missing the pre reloc bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Jan Viktorin <viktorin@rehivetech.com>
2015-11-23 17:06:27 +01:00
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
arm: socfpga: Add SoCFPGA SR1500 board The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices: - SPI NOR - eMMC - Ethernet Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
2015-11-18 11:06:09 +01:00
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
arm: socfpga: Add samtec VIN|ING board Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- V2: Update the defconfig as per Tom's request
2015-12-01 18:09:52 +01:00
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 20:38:20 +09:00
endif
Reference in a new issue Copy permalink