u-boot/arch/arm/cpu/armv8/spin_table_v8.S

/*
 * Copyright (C) 2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <linux/linkage.h>

ENTRY(spin_table_secondary_jump)
.globl spin_table_reserve_begin
spin_table_reserve_begin:
0:	wfe
	ldr	x0, spin_table_cpu_release_addr
	cbz	x0, 0b
	br	x0
.globl spin_table_cpu_release_addr
	.align	3
spin_table_cpu_release_addr:
	.quad	0
.globl spin_table_reserve_end
spin_table_reserve_end:
ENDPROC(spin_table_secondary_jump)
arm64: add better and more generic spin-table support There are two enable methods supported by ARM64 Linux; psci and spin-table. The latter is simpler and helpful for quick SoC bring up. My main motivation for this patch is to improve the spin-table support, which allows us to boot an ARMv8 system without the ARM Trusted Firmware. Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S and the spin-table is supported in a really ad-hoc way, and I see some problems: - We must hard-code CPU_RELEASE_ADDR so that it matches the "cpu-release-addr" property in the DT that comes from the kernel tree. - The Documentation/arm64/booting.txt in Linux requires that the release address must be zero-initialized, but it is not cared by the common code in U-Boot. We must do it in a board function. - There is no systematic way to protect the spin-table code from the kernel. We are supposed to do it in a board specific manner, but it is difficult to predict where the spin-table code will be located after the relocation. So, it also makes difficult to hard-code /memreserve/ in the DT of the kernel. So, here is a patch to solve those problems; the DT is run-time modified to reserve the spin-table code (+ cpu-release-addr). Also, the "cpu-release-addr" property is set to an appropriate address after the relocation, which means we no longer need the hard-coded CPU_RELEASE_ADDR. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 2016-06-27 10:31:05 +00:00			`/*`
			`* Copyright (C) 2016 Socionext Inc.`
			`* Author: Masahiro Yamada <yamada.masahiro@socionext.com>`
			`*`
			`* SPDX-License-Identifier: GPL-2.0+`
			`*/`

			`#include <linux/linkage.h>`

			`ENTRY(spin_table_secondary_jump)`
			`.globl spin_table_reserve_begin`
			`spin_table_reserve_begin:`
			`0: wfe`
			`ldr x0, spin_table_cpu_release_addr`
			`cbz x0, 0b`
			`br x0`
			`.globl spin_table_cpu_release_addr`
			`.align 3`
			`spin_table_cpu_release_addr:`
			`.quad 0`
			`.globl spin_table_reserve_end`
			`spin_table_reserve_end:`
			`ENDPROC(spin_table_secondary_jump)`