2018-05-06 17:58:06 -04:00
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// SPDX-License-Identifier: GPL-2.0+
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2016-03-31 23:12:16 +02:00
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/*
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* Qualcomm SDHCI driver - SD/eMMC controller
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*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*
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* Based on Linux driver
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*/
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#include <clk.h>
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#include <dm.h>
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2020-02-03 07:36:16 -07:00
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#include <malloc.h>
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2016-03-31 23:12:16 +02:00
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#include <sdhci.h>
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#include <wait_bit.h>
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2020-10-30 21:38:53 -06:00
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#include <asm/global_data.h>
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2016-03-31 23:12:16 +02:00
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#include <asm/io.h>
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#include <linux/bitops.h>
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2024-10-16 11:17:16 +02:00
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#include <power/regulator.h>
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2016-03-31 23:12:16 +02:00
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/* Non-standard registers needed for SDHCI startup */
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#define SDCC_MCI_POWER 0x0
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#define SDCC_MCI_POWER_SW_RST BIT(7)
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/* This is undocumented register */
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2022-07-12 12:42:09 +05:30
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#define SDCC_MCI_VERSION 0x50
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#define SDCC_V5_VERSION 0x318
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#define SDCC_VERSION_MAJOR_SHIFT 28
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#define SDCC_VERSION_MAJOR_MASK (0xf << SDCC_VERSION_MAJOR_SHIFT)
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#define SDCC_VERSION_MINOR_MASK 0xff
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2016-03-31 23:12:16 +02:00
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#define SDCC_MCI_STATUS2 0x6C
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#define SDCC_MCI_STATUS2_MCI_ACT 0x1
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#define SDCC_MCI_HC_MODE 0x78
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2024-06-21 03:53:09 +02:00
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#define CORE_VENDOR_SPEC_POR_VAL 0xa9c
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2016-06-12 23:30:29 -06:00
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struct msm_sdhc_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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2016-03-31 23:12:16 +02:00
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struct msm_sdhc {
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struct sdhci_host host;
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void *base;
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2024-02-26 17:26:07 +00:00
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struct clk_bulk clks;
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2024-10-16 11:17:16 +02:00
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struct udevice *vqmmc;
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2016-03-31 23:12:16 +02:00
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};
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2022-07-12 12:42:09 +05:30
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struct msm_sdhc_variant_info {
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bool mci_removed;
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2024-04-09 20:03:00 +02:00
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2024-06-21 03:53:09 +02:00
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u32 core_vendor_spec;
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2024-04-09 20:03:00 +02:00
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u32 core_vendor_spec_capabilities0;
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2022-07-12 12:42:09 +05:30
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};
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2016-03-31 23:12:16 +02:00
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DECLARE_GLOBAL_DATA_PTR;
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static int msm_sdc_clk_init(struct udevice *dev)
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{
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2024-02-26 17:26:07 +00:00
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struct msm_sdhc *prv = dev_get_priv(dev);
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2024-06-21 03:53:09 +02:00
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const struct msm_sdhc_variant_info *var_info;
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2024-02-26 17:26:07 +00:00
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ofnode node = dev_ofnode(dev);
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ulong clk_rate;
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int ret, i = 0, n_clks;
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const char *clk_name;
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2016-03-31 23:12:16 +02:00
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2024-06-21 03:53:09 +02:00
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var_info = (void *)dev_get_driver_data(dev);
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2024-02-26 17:26:07 +00:00
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ret = ofnode_read_u32(node, "clock-frequency", (uint *)(&clk_rate));
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2016-03-31 23:12:16 +02:00
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if (ret)
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2024-04-09 20:03:03 +02:00
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clk_rate = 201500000;
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2016-03-31 23:12:16 +02:00
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2024-02-26 17:26:07 +00:00
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ret = clk_get_bulk(dev, &prv->clks);
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if (ret) {
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log_warning("Couldn't get mmc clocks: %d\n", ret);
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2016-03-31 23:12:16 +02:00
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return ret;
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2024-02-26 17:26:07 +00:00
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}
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2016-03-31 23:12:16 +02:00
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2024-02-26 17:26:07 +00:00
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ret = clk_enable_bulk(&prv->clks);
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if (ret) {
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log_warning("Couldn't enable mmc clocks: %d\n", ret);
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2016-06-17 09:44:00 -06:00
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return ret;
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2024-02-26 17:26:07 +00:00
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}
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2016-06-17 09:44:00 -06:00
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2024-02-26 17:26:07 +00:00
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/* If clock-names is unspecified, then the first clock is the core clock */
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if (!ofnode_get_property(node, "clock-names", &n_clks)) {
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if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) {
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log_warning("Couldn't set core clock rate: %d\n", ret);
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return -EINVAL;
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}
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}
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/* Find the index of the "core" clock */
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while (i < n_clks) {
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ofnode_read_string_index(node, "clock-names", i, &clk_name);
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if (!strcmp(clk_name, "core"))
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break;
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i++;
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}
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if (i >= prv->clks.count) {
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log_warning("Couldn't find core clock (index %d but only have %d clocks)\n", i,
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prv->clks.count);
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return -EINVAL;
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}
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/* The clock is already enabled by the clk_bulk above */
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clk_rate = clk_set_rate(&prv->clks.clks[i], clk_rate);
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/* If we get a rate of 0 then something has probably gone wrong. */
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if (clk_rate == 0 || IS_ERR((void *)clk_rate)) {
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log_warning("Couldn't set MMC core clock rate: %dE\n", clk_rate ? (int)PTR_ERR((void *)clk_rate) : 0);
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return -EINVAL;
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}
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2016-03-31 23:12:16 +02:00
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2024-06-21 03:53:09 +02:00
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writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
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prv->host.ioaddr + var_info->core_vendor_spec);
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2016-03-31 23:12:16 +02:00
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return 0;
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}
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2022-07-12 12:42:09 +05:30
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static int msm_sdc_mci_init(struct msm_sdhc *prv)
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2016-03-31 23:12:16 +02:00
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{
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/* Reset the core and Enable SDHC mode */
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writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
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prv->base + SDCC_MCI_POWER);
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/* Wait for reset to be written to register */
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2018-01-23 17:14:55 +01:00
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if (wait_for_bit_le32(prv->base + SDCC_MCI_STATUS2,
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SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) {
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2016-03-31 23:12:16 +02:00
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printf("msm_sdhci: reset request failed\n");
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return -EIO;
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}
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/* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
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2018-01-23 17:14:55 +01:00
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if (wait_for_bit_le32(prv->base + SDCC_MCI_POWER,
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SDCC_MCI_POWER_SW_RST, false, 2, false)) {
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2016-03-31 23:12:16 +02:00
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printf("msm_sdhci: stuck in reset\n");
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return -ETIMEDOUT;
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}
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/* Enable host-controller mode */
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writel(1, prv->base + SDCC_MCI_HC_MODE);
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2022-07-12 12:42:09 +05:30
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return 0;
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}
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2016-03-31 23:12:16 +02:00
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2022-07-12 12:42:09 +05:30
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static int msm_sdc_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct msm_sdhc_plat *plat = dev_get_plat(dev);
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struct msm_sdhc *prv = dev_get_priv(dev);
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const struct msm_sdhc_variant_info *var_info;
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struct sdhci_host *host = &prv->host;
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u32 core_version, core_minor, core_major;
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u32 caps;
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int ret;
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2016-03-31 23:12:16 +02:00
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2022-07-12 12:42:09 +05:30
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host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
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host->max_clk = 0;
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/* Init clocks */
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ret = msm_sdc_clk_init(dev);
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if (ret)
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return ret;
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2024-10-16 11:17:16 +02:00
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/* Get the vqmmc regulator and enable it if available */
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device_get_supply_regulator(dev, "vqmmc-supply", &prv->vqmmc);
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if (prv->vqmmc) {
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ret = regulator_set_enable_if_allowed(prv->vqmmc, true);
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if (ret) {
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printf("Failed to enable the VQMMC regulator\n");
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return ret;
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}
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}
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2022-07-12 12:42:09 +05:30
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var_info = (void *)dev_get_driver_data(dev);
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if (!var_info->mci_removed) {
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ret = msm_sdc_mci_init(prv);
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if (ret)
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return ret;
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}
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if (!var_info->mci_removed)
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core_version = readl(prv->base + SDCC_MCI_VERSION);
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else
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core_version = readl(host->ioaddr + SDCC_V5_VERSION);
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core_major = (core_version & SDCC_VERSION_MAJOR_MASK);
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core_major >>= SDCC_VERSION_MAJOR_SHIFT;
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core_minor = core_version & SDCC_VERSION_MINOR_MASK;
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2016-03-31 23:12:16 +02:00
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2024-04-09 20:03:02 +02:00
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log_debug("SDCC version %d.%d\n", core_major, core_minor);
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2016-03-31 23:12:16 +02:00
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/*
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* Support for some capabilities is not advertised by newer
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* controller versions and must be explicitly enabled.
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*/
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if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
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2016-06-12 23:30:29 -06:00
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caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
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2016-03-31 23:12:16 +02:00
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caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
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2024-04-09 20:03:00 +02:00
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writel(caps, host->ioaddr + var_info->core_vendor_spec_capabilities0);
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2016-03-31 23:12:16 +02:00
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}
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2020-07-16 14:37:26 +05:30
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ret = mmc_of_parse(dev, &plat->cfg);
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if (ret)
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return ret;
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2016-06-12 23:30:29 -06:00
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host->mmc = &plat->mmc;
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2019-08-06 02:47:53 +00:00
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host->mmc->dev = dev;
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ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
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2016-06-26 22:43:55 +02:00
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if (ret)
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return ret;
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2016-06-12 23:30:29 -06:00
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host->mmc->priv = &prv->host;
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upriv->mmc = host->mmc;
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2016-06-26 22:43:55 +02:00
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2016-06-12 23:30:29 -06:00
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return sdhci_probe(dev);
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2016-03-31 23:12:16 +02:00
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}
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static int msm_sdc_remove(struct udevice *dev)
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{
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struct msm_sdhc *priv = dev_get_priv(dev);
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2022-07-12 12:42:09 +05:30
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const struct msm_sdhc_variant_info *var_info;
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var_info = (void *)dev_get_driver_data(dev);
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2016-03-31 23:12:16 +02:00
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2022-07-12 12:42:09 +05:30
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/* Disable host-controller mode */
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2024-04-09 20:03:01 +02:00
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if (!var_info->mci_removed && priv->base)
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2022-07-12 12:42:09 +05:30
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writel(0, priv->base + SDCC_MCI_HC_MODE);
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2016-03-31 23:12:16 +02:00
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2024-02-26 17:26:07 +00:00
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clk_release_bulk(&priv->clks);
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2016-03-31 23:12:16 +02:00
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return 0;
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}
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2020-12-03 16:55:21 -07:00
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static int msm_of_to_plat(struct udevice *dev)
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2016-03-31 23:12:16 +02:00
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{
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struct msm_sdhc *priv = dev_get_priv(dev);
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2024-04-09 20:03:01 +02:00
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const struct msm_sdhc_variant_info *var_info;
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2016-03-31 23:12:16 +02:00
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struct sdhci_host *host = &priv->host;
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2024-04-09 20:03:01 +02:00
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int ret;
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var_info = (void*)dev_get_driver_data(dev);
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2016-03-31 23:12:16 +02:00
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host->name = strdup(dev->name);
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2020-07-17 14:36:46 +09:00
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host->ioaddr = dev_read_addr_ptr(dev);
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2024-04-09 20:03:01 +02:00
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ret = dev_read_u32(dev, "bus-width", &host->bus_width);
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if (ret)
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host->bus_width = 4;
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ret = dev_read_u32(dev, "index", &host->index);
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if (ret)
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host->index = 0;
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priv->base = dev_read_addr_index_ptr(dev, 1);
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if (!host->ioaddr)
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2016-03-31 23:12:16 +02:00
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return -EINVAL;
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2024-04-09 20:03:01 +02:00
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if (!var_info->mci_removed && !priv->base) {
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printf("msm_sdhci: MCI base address not found\n");
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return -EINVAL;
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}
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2016-03-31 23:12:16 +02:00
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return 0;
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}
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2016-06-12 23:30:29 -06:00
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static int msm_sdc_bind(struct udevice *dev)
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{
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2020-12-03 16:55:20 -07:00
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struct msm_sdhc_plat *plat = dev_get_plat(dev);
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2016-06-12 23:30:29 -06:00
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2016-09-06 22:17:32 +09:00
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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2016-06-12 23:30:29 -06:00
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}
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2022-07-12 12:42:09 +05:30
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static const struct msm_sdhc_variant_info msm_sdhc_mci_var = {
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.mci_removed = false,
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2024-04-09 20:03:00 +02:00
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2024-06-21 03:53:09 +02:00
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.core_vendor_spec = 0x10c,
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2024-04-12 20:10:21 +02:00
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.core_vendor_spec_capabilities0 = 0x11c,
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2022-07-12 12:42:09 +05:30
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};
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static const struct msm_sdhc_variant_info msm_sdhc_v5_var = {
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.mci_removed = true,
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2024-04-09 20:03:00 +02:00
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2024-06-21 03:53:09 +02:00
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.core_vendor_spec = 0x20c,
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2024-04-12 20:10:21 +02:00
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.core_vendor_spec_capabilities0 = 0x21c,
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2022-07-12 12:42:09 +05:30
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};
|
|
|
|
|
2016-03-31 23:12:16 +02:00
|
|
|
static const struct udevice_id msm_mmc_ids[] = {
|
2022-07-12 12:42:09 +05:30
|
|
|
{ .compatible = "qcom,sdhci-msm-v4", .data = (ulong)&msm_sdhc_mci_var },
|
|
|
|
{ .compatible = "qcom,sdhci-msm-v5", .data = (ulong)&msm_sdhc_v5_var },
|
2016-03-31 23:12:16 +02:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(msm_sdc_drv) = {
|
|
|
|
.name = "msm_sdc",
|
|
|
|
.id = UCLASS_MMC,
|
|
|
|
.of_match = msm_mmc_ids,
|
2020-12-03 16:55:21 -07:00
|
|
|
.of_to_plat = msm_of_to_plat,
|
2016-06-12 23:30:29 -06:00
|
|
|
.ops = &sdhci_ops,
|
|
|
|
.bind = msm_sdc_bind,
|
2016-03-31 23:12:16 +02:00
|
|
|
.probe = msm_sdc_probe,
|
|
|
|
.remove = msm_sdc_remove,
|
2020-12-03 16:55:17 -07:00
|
|
|
.priv_auto = sizeof(struct msm_sdhc),
|
2020-12-03 16:55:18 -07:00
|
|
|
.plat_auto = sizeof(struct msm_sdhc_plat),
|
2016-03-31 23:12:16 +02:00
|
|
|
};
|