mirror of
https://github.com/AsahiLinux/m1n1
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88 lines
2.5 KiB
C
88 lines
2.5 KiB
C
/* SPDX-License-Identifier: MIT */
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#ifndef MEMORY_H
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#define MEMORY_H
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#include "cpu_regs.h"
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#include "types.h"
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#define REGION_RWX_EL0 0x80000000000
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#define REGION_RW_EL0 0xa0000000000
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#define REGION_RX_EL1 0xc0000000000
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/*
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* https://armv8-ref.codingbelief.com/en/chapter_d4/d43_2_armv8_translation_table_level_3_descriptor_formats.html
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* PTE_TYPE:PTE_BLOCK indicates that the page table entry (PTE) points to a physical memory block
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* PTE_TYPE:PTE_TABLE indicates that the PTE points to another PTE
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* PTE_TYPE:PTE_PAGE indicates that the PTE points to a single page
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* PTE_FLAG_ACCESS is required to allow access to the memory region
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* PTE_MAIR_IDX sets the MAIR index to be used for this PTE
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*/
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#define PTE_VALID BIT(0)
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#define PTE_TYPE BIT(1)
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#define PTE_BLOCK 0
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#define PTE_TABLE 1
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#define PTE_PAGE 1
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#define PTE_ACCESS BIT(10)
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#define PTE_MAIR_IDX(i) ((i & 7) << 2)
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#define PTE_PXN BIT(53)
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#define PTE_UXN BIT(54)
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#define PTE_AP_RO BIT(7)
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#define PTE_AP_EL0 BIT(6)
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#define PTE_SH_NS (0b00 << 8)
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#define PTE_SH_OS (0b10 << 8)
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#define PTE_SH_IS (0b11 << 8)
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#define PERM_RO_EL0 PTE_AP_EL0 | PTE_AP_RO | PTE_PXN | PTE_UXN
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#define PERM_RW_EL0 PTE_AP_EL0 | PTE_PXN | PTE_UXN
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#define PERM_RX_EL0 PTE_AP_EL0 | PTE_AP_RO
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#define PERM_RWX_EL0 PTE_AP_EL0
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#define PERM_RO PTE_AP_RO | PTE_PXN | PTE_UXN
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#define PERM_RW PTE_PXN | PTE_UXN
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#define PERM_RX PTE_AP_RO | PTE_UXN
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#define PERM_RWX 0
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#define MAIR_IDX_NORMAL 0
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#define MAIR_IDX_NORMAL_NC 1
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#define MAIR_IDX_DEVICE_nGnRnE 2
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#define MAIR_IDX_DEVICE_nGnRE 3
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#define MAIR_IDX_DEVICE_nGRE 4
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#define MAIR_IDX_DEVICE_GRE 5
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#ifndef __ASSEMBLER__
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#include "utils.h"
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extern uint64_t ram_base;
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void ic_ivau_range(void *addr, size_t length);
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void dc_ivac_range(void *addr, size_t length);
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void dc_zva_range(void *addr, size_t length);
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void dc_cvac_range(void *addr, size_t length);
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void dc_cvau_range(void *addr, size_t length);
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void dc_civac_range(void *addr, size_t length);
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#define DCSW_OP_DCISW 0x0
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#define DCSW_OP_DCCISW 0x1
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#define DCSW_OP_DCCSW 0x2
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void dcsw_op_all(u64 op_type);
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void mmu_init(void);
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void mmu_init_secondary(int cpu);
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void mmu_shutdown(void);
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void mmu_add_mapping(u64 from, u64 to, size_t size, u8 attribute_index, u64 perms);
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void mmu_rm_mapping(u64 from, size_t size);
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void mmu_map_framebuffer(u64 addr, size_t size);
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u64 mmu_disable(void);
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void mmu_restore(u64 state);
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static inline bool mmu_active(void)
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{
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return mrs(SCTLR_EL1) & SCTLR_M;
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}
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#endif
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#endif
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