mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-27 00:40:17 +00:00
132 lines
3.7 KiB
Python
Executable file
132 lines
3.7 KiB
Python
Executable file
#!/usr/bin/env python3
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# SPDX-License-Identifier: MIT
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import sys, pathlib
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import time
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sys.path.append(str(pathlib.Path(__file__).resolve().parents[1]))
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# audio_capture.py -- capture audio on jack microphone input (on M1 macs with cs42l83)
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#
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# sample usage with sox: (recoding can be loud!)
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#
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# ./audio_capture.py | sox -t raw -r 48000 -c 1 -e signed-int -b 32 -L - OUTPUT_FILE
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from m1n1.setup import *
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from m1n1.hw.dart import DART, DARTRegs
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from m1n1.hw.i2c import I2C
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from m1n1.hw.pmgr import PMGR
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from m1n1.hw.nco import NCO
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from m1n1.hw.admac import *
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from m1n1.hw.mca import *
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p.pmgr_adt_clocks_enable("/arm-io/i2c2")
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p.pmgr_adt_clocks_enable("/arm-io/admac-sio")
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p.pmgr_adt_clocks_enable("/arm-io/dart-sio")
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p.pmgr_adt_clocks_enable("/arm-io/mca-switch")
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p.pmgr_adt_clocks_enable("/arm-io/mca3")
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# reset AUDIO_P
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PS_AUDIO_P = PMGR(u).regs[0].PS4[10]
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PS_AUDIO_P.set(DEV_DISABLE=1)
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PS_AUDIO_P.set(RESET=1)
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PS_AUDIO_P.set(RESET=0)
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PS_AUDIO_P.set(DEV_DISABLE=0)
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dart_base, _ = u.adt["/arm-io/dart-sio"].get_reg(0)
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dart = DART(iface, DARTRegs(u, dart_base), util=u)
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dart.initialize()
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cl_no = 2
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admac = ADMAC(u, "/arm-io/admac-sio", dart, debug=True)
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dmachan = admac.chans[4*cl_no+1]
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dmachan.buswidth = E_BUSWIDTH.W_32BIT
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dmachan.framesize = E_FRAME.F_1_WORD
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nco = NCO(u, "/arm-io/nco")
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nco[cl_no].set_rate(6000000)
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nco[cl_no].enable()
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mca_switch1_base = u.adt["/arm-io/mca-switch"].get_reg(1)[0]
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mca_cl_base = u.adt["/arm-io/mca-switch"].get_reg(0)[0] + 0x4000*cl_no
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cl = MCACluster(u, mca_cl_base)
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regs, serdes = cl.regs, cl.rxa
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regs.SYNCGEN_STATUS.set(EN=0)
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regs.SYNCGEN_MCLK_SEL.val =(1 + cl_no)
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regs.SYNCGEN_HI_PERIOD.val = 0 # period minus one
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regs.SYNCGEN_LO_PERIOD.val = 0x7b # period minus one
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serdes.STATUS.set(EN=0)
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serdes.CONF.set(
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NSLOTS=0,
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SLOT_WIDTH=E_SLOT_WIDTH.W_32BIT,
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BCLK_POL=1,
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UNK1=1, UNK2=1,
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SYNC_SEL=(1 + cl_no)
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)
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serdes.UNK1.val = 0x4
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serdes.BITDELAY.val = 1
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serdes.CHANMASK[0].val = 0xffff_ffff
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serdes.CHANMASK[1].val = 0xffff_fffe
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regs.PORT_ENABLES.set(CLOCK1=1, CLOCK2=1, DATA=0)
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regs.PORT_CLK_SEL.set(SEL=(cl_no + 1))
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regs.MCLK_STATUS.set(EN=1)
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regs.SYNCGEN_STATUS.set(EN=1)
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cs42l_addr = 0x48
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i2c2 = I2C(u, "/arm-io/i2c2")
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def cs42l_write(regaddr, val):
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i2c2.write_reg(cs42l_addr, 0x0, [regaddr >> 8])
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i2c2.write_reg(cs42l_addr, regaddr & 0xff, [val])
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p.write32(0x23d1f002c, 0x76a02)
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p.write32(0x23d1f002c, 0x76a03) # take jack codec out of reset
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cs42l_write(0x1009, 0x0) # FS_int = MCLK/250
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cs42l_write(0x1101, 0x7a) # power on
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cs42l_write(0x1103, 0x22) # power on ring sense
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cs42l_write(0x1107, 0x1) # SCLK present
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cs42l_write(0x1121, 0xa6) # Headset Switch Control
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cs42l_write(0x1129, 0x1) # Headset Clamp Disable
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cs42l_write(0x1205, 0x7c) # FSYNC period
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cs42l_write(0x1207, 0x20) # ASP Clock Configuration
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cs42l_write(0x1208, 0x12) # BITDELAY = 1
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cs42l_write(0x120c, 0x1) # SCLK_PREDIV = div-by-2
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cs42l_write(0x150a, 0x55) # PLL
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cs42l_write(0x151b, 0x1) # PLL
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cs42l_write(0x1501, 0x1) # power on PLL
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cs42l_write(0x1b70, 0xc3) # HSBIAS sense
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cs42l_write(0x1b71, 0xe0) # v-- headset
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cs42l_write(0x1b73, 0xc0)
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cs42l_write(0x1b74, 0x1f)
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cs42l_write(0x1b75, 0xb6)
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cs42l_write(0x1b76, 0x8f)
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cs42l_write(0x1b79, 0x0)
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cs42l_write(0x1b7a, 0xfc)
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cs42l_write(0x1c03, 0xc0) # HSBIAS
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cs42l_write(0x2506, 0xc) # ASP TX samp. rate
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cs42l_write(0x2609, 0x4c) # SRC output samp. rate
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cs42l_write(0x2901, 0x1) # ASP TX enable & size
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cs42l_write(0x2902, 0x1) # ASP TX channel enable
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time.sleep(0.01)
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cs42l_write(0x1201, 0x1) # transition to PLL clock
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# drain garbled samples (why are they garbled? i am not sure)
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time.sleep(0.5)
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dmachan.submit(buflen=0x4000)
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dmachan.enable()
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p.write32(mca_switch1_base + 0x8000*cl_no, 0x24800)
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serdes.STATUS.set(EN=1)
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while True:
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while dmachan.can_submit():
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dmachan.submit(buflen=0x4000)
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sys.stdout.buffer.write(dmachan.poll())
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