mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-09-21 13:41:54 +00:00
d9561b7507
All the common/importable stuff now lives in the 'm1n1' module. General use tools are in tools/ Reverse engineering experiments are in experiments/ Signed-off-by: Hector Martin <marcan@marcan.st>
108 lines
2.5 KiB
Python
Executable file
108 lines
2.5 KiB
Python
Executable file
#!/usr/bin/env python3
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# SPDX-License-Identifier: MIT
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import sys, pathlib
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sys.path.append(str(pathlib.Path(__file__).resolve().parents[1]))
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from m1n1.setup import *
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sys_regs = dict([
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("HID0", (3, 0, 15, 0, 0)),
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("HID1", (3, 0, 15, 1, 0)),
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("EHID20", (3, 0, 15, 1, 2)),
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("HID2", (3, 0, 15, 2, 0)),
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("HID3", (3, 0, 15, 3, 0)),
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("HID4", (3, 0, 15, 4, 0)),
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("EHID4", (3, 0, 15, 4, 1)),
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("HID5", (3, 0, 15, 5, 0)),
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("HID6", (3, 0, 15, 6, 0)),
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("HID7", (3, 0, 15, 7, 0)),
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("HID8", (3, 0, 15, 8, 0)),
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("HID9", (3, 0, 15, 9, 0)),
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("EHID9", (3, 0, 15, 9, 1)),
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("HID10", (3, 0, 15, 10, 0)),
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("EHID10", (3, 0, 15, 10, 1)),
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("HID11", (3, 0, 15, 11, 0)),
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])
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CYC_OVRD = (3, 5, 15, 5, 0)
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CYC_CFG = (3, 5, 15, 4, 0)
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L2C_ERR_STS = (3, 3, 15, 8, 0)
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s3_6_c15_c1_0 = (3, 6, 15, 1, 0)
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s3_6_c15_c1_6 = (3, 6, 15, 1, 6)
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s3_4_c15_c1_4 = (3, 4, 15, 1, 4)
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s3_4_c15_c5_0 = (3, 4, 15, 5, 0)
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h13e_chickenbits = [
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("EHID4", 0x100000000800, 0),
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("HID5", 0x2000000000000000, 0),
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("EHID10", 0x2000100000000, 0),
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("EHID20", 0x100, 0),
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("EHID9", 0, 0x20),
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("EHID20", 0x8000, 0),
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("EHID20", 0x10000, 0),
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("EHID20", 0x600000, 0),
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]
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tlbi_vmalle1 = 0xd508871f
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def h13e_init():
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mpidr = u.mrs(MPIDR_EL1)
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print("mpidr = 0x%x" % mpidr)
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#print("OSLAR")
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#u.msr(OSLAR_EL1, 0)
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#print("s3_6_c15_c1_0")
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#u.msr(s3_6_c15_c1_0, 1)
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#print("tlbi_vmalle1")
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#u.inst(tlbi_vmalle1)
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## This looks like APRR stuff?
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#v = u.mrs(s3_6_c15_c1_6)
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#print("s3_6_c15_c1_6 == 0x%x" % v)
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#v = 0x2020a505f020f0f0
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#print("s3_6_c15_c1_6 <= 0x%x" % v)
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#u.msr(s3_6_c15_c1_6, v)
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#u.msr(s3_6_c15_c1_0, 0)
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for reg, setb, clearb in h13e_chickenbits:
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v = u.mrs(sys_regs[reg])
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print("%r == 0x%x" % (reg, v))
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v &= ~clearb
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v |= setb
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print("%r <= 0x%x" % (reg, v))
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u.msr(sys_regs[reg], v)
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v = u.mrs(s3_4_c15_c5_0)
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print("s3_4_c15_c5_0 == 0x%x" % v)
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print("s3_4_c15_c5_0 <= 0x%x" % (mpidr & 0xff))
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u.msr(s3_4_c15_c5_0, mpidr & 0xff)
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u.msr(s3_4_c15_c1_4, 0x100)
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v = u.mrs(CYC_OVRD)
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print("CYC_OVRD == 0x%x" % v)
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v &= ~0xf00000
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print("CYC_OVRD <= 0x%x" % v)
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u.msr(CYC_OVRD, v)
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v = u.mrs(ACTLR_EL1)
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print("ACTLR_EL1 == 0x%x" % v)
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v |= 0x200
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print("ACTLR_EL1 <= 0x%x" % v)
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u.msr(ACTLR_EL1, v)
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v = u.mrs(CYC_CFG)
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print("CYC_CFG == 0x%x" % v)
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v |= 0xc
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print("CYC_CFG <= 0x%x" % v)
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u.msr(CYC_CFG, v)
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print("L2C_ERR_STS = %x" % u.mrs(L2C_ERR_STS))
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u.msr(L2C_ERR_STS, 0)
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h13e_init()
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