mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-26 16:30:17 +00:00
cfe597e447
vector() does not expect a reply, reboot() expects a hello reply. Signed-off-by: Hector Martin <marcan@marcan.st>
502 lines
15 KiB
Python
Executable file
502 lines
15 KiB
Python
Executable file
#!/usr/bin/python3
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# SPDX-License-Identifier: MIT
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import os, sys, struct
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def hexdump(s, sep=" "):
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return sep.join(["%02x"%x for x in s])
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def hexdump32(s, sep=" "):
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vals = struct.unpack("<%dI" % (len(s)//4), s)
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return sep.join(["%08x"%x for x in vals])
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def ascii(s):
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s2 = ""
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for c in s:
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if c < 0x20 or c > 0x7e:
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s2 += "."
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else:
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s2 += c
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return s2
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def pad(s,c,l):
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if len(s) < l:
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s += c * (l - len(s))
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return s
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def chexdump(s,st=0):
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for i in range(0,len(s),16):
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print("%08x %s %s |%s|" % (
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i + st,
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hexdump(s[i:i+8], ' ').rjust(23),
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hexdump(s[i+8:i+16], ' ').rjust(23),
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ascii(s[i:i+16]),rjust(16)))
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def chexdump32(s, st=0, abbreviate=True):
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last = None
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skip = False
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for i in range(0,len(s),32):
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val = s[i:i+32]
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if val == last and abbreviate:
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if not skip:
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print("%08x *" % (i + st))
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skip = True
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else:
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print("%08x %s" % (
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i + st,
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hexdump32(val, ' ')))
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last = val
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skip = False
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class UartError(RuntimeError):
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pass
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class UartTimeout(UartError):
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pass
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class UartCMDError(UartError):
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pass
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class UartChecksumError(UartError):
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pass
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class UartRemoteError(UartError):
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pass
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class UartInterface:
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REQ_NOP = 0x00AA55FF
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REQ_PROXY = 0x01AA55FF
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REQ_MEMREAD = 0x02AA55FF
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REQ_MEMWRITE = 0x03AA55FF
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REQ_BOOT = 0x04AA55FF
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ST_OK = 0
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ST_BADCMD = -1
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ST_INVAL = -2
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ST_XFERERR = -3
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ST_CRCERR = -4
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CMD_LEN = 56
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REPLY_LEN = 36
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def __init__(self, device, debug=False):
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self.debug = debug
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self.dev = device
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self.dev.timeout = 0
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self.dev.flushOutput()
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self.dev.flushInput()
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self.pted = False
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#d = self.dev.read(1)
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#while d != "":
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#d = self.dev.read(1)
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self.dev.timeout = 3
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self.tty_enable = True
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def checksum(self, data):
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sum = 0xDEADBEEF;
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for c in data:
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sum *= 31337
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sum += c ^ 0x5a
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sum &= 0xFFFFFFFF
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return (sum ^ 0xADDEDBAD) & 0xFFFFFFFF
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def readfull(self, size):
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d = b''
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while len(d) < size:
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block = self.dev.read(size - len(d))
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if not block:
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raise UartTimeout("Expected %d bytes, got %d bytes"%(size,len(d)))
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d += block
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return d
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def cmd(self, cmd, payload=b""):
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if len(payload) > self.CMD_LEN:
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raise ValueError("Incorrect payload size %d"%len(payload))
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payload = payload.ljust(self.CMD_LEN, b"\x00")
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command = struct.pack("<I", cmd) + payload
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command += struct.pack("<I", self.checksum(command))
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if self.debug:
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print("<<", hexdump(command))
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self.dev.write(command)
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def unkhandler(self, s):
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if not self.tty_enable:
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return
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for c in s:
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if not self.pted:
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sys.stdout.write("TTY> ")
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self.pted = True
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if c == 10:
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self.pted = False
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sys.stdout.write(chr(c))
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sys.stdout.flush()
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def reply(self, cmd):
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reply = b''
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while True:
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if not reply or reply[-1] != 255:
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reply = b''
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reply += self.readfull(1)
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if reply != b"\xff":
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self.unkhandler(reply)
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continue
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else:
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reply = b'\xff'
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reply += self.readfull(1)
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if reply != b"\xff\x55":
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self.unkhandler(reply)
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continue
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reply += self.readfull(1)
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if reply != b"\xff\x55\xaa":
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self.unkhandler(reply)
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continue
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reply += self.readfull(self.REPLY_LEN - 3)
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if self.debug:
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print(">>", hexdump(reply))
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cmdin, status, data, checksum = struct.unpack("<Ii24sI", reply)
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ccsum = self.checksum(reply[:-4])
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if checksum != ccsum:
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print("Reply checksum error: Expected 0x%08x, got 0x%08x"%(checksum, ccsum))
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raise UartChecksumError()
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if cmdin != cmd:
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if cmdin == self.REQ_BOOT:
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# Proxy rebooted in the meantime, try again
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return self.reply(cmd)
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raise UartCMDError("Reply command mismatch: Expected 0x%08x, got 0x%08x"%(cmd, cmdin))
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if status != self.ST_OK:
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if status == self.ST_BADCMD:
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raise UartRemoteError("Reply error: Bad Command")
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elif status == self.ST_INVAL:
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raise UartRemoteError("Reply error: Invalid argument")
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elif status == self.ST_XFERERR:
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raise UartRemoteError("Reply error: Data transfer failed")
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elif status == self.ST_CRCERR:
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raise UartRemoteError("Reply error: Data checksum failed")
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else:
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raise UartRemoteError("Reply error: Unknown error (%d)"%status)
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return data
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def nop(self):
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self.cmd(self.REQ_NOP)
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self.reply(self.REQ_NOP)
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def proxyreq(self, req, reboot=False, no_reply=False):
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self.cmd(self.REQ_PROXY, req)
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if no_reply:
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return
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elif reboot:
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return self.reply(self.REQ_BOOT)
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else:
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return self.reply(self.REQ_PROXY)
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def writemem(self, addr, data, progress=False):
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checksum = self.checksum(data)
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size = len(data)
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req = struct.pack("<QQI", addr, size, checksum)
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self.cmd(self.REQ_MEMWRITE, req)
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if self.debug:
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print("<< DATA:")
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chexdump(data)
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for i in range(0, len(data), 8192):
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self.dev.write(data[i:i + 8192])
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if progress:
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sys.stdout.write(".")
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sys.stdout.flush()
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if progress:
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print()
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# should automatically report a CRC failure
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self.reply(self.REQ_MEMWRITE)
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def readmem(self, addr, size):
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req = struct.pack("<QQ", addr, size)
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self.cmd(self.REQ_MEMREAD, req)
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reply = self.reply(self.REQ_MEMREAD)
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checksum = struct.unpack("<I",reply[:4])[0]
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data = self.readfull(size)
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if self.debug:
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print(">> DATA:")
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chexdump(data)
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ccsum = self.checksum(data)
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if checksum != ccsum:
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raise UartCRCError("Reply data checksum error: Expected 0x%08x, got 0x%08x"%(checksum, ccsum))
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return data
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def readstruct(self, addr, stype):
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return stype.parse(self.readmem(addr, stype.sizeof()))
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class ProxyError(RuntimeError):
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pass
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class ProxyCMDError(ProxyError):
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pass
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class ProxyRemoteError(ProxyError):
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pass
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class AlignmentError(Exception):
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pass
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class M1N1Proxy:
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S_OK = 0
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S_BADCMD = -1
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P_NOP = 0x000
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P_EXIT = 0x001
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P_CALL = 0x002
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P_GET_BOOTARGS = 0x003
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P_GET_BASE = 0x004
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P_SET_BAUD = 0x005
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P_WRITE64 = 0x100
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P_WRITE32 = 0x101
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P_WRITE16 = 0x102
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P_WRITE8 = 0x103
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P_READ64 = 0x104
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P_READ32 = 0x105
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P_READ16 = 0x106
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P_READ8 = 0x107
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P_SET64 = 0x108
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P_SET32 = 0x109
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P_SET16 = 0x10a
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P_SET8 = 0x10b
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P_CLEAR64 = 0x10c
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P_CLEAR32 = 0x10d
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P_CLEAR16 = 0x10e
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P_CLEAR8 = 0x10f
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P_MASK64 = 0x110
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P_MASK32 = 0x111
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P_MASK16 = 0x112
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P_MASK8 = 0x113
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P_MEMCPY64 = 0x200
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P_MEMCPY32 = 0x201
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P_MEMCPY16 = 0x202
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P_MEMCPY8 = 0x203
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P_MEMSET64 = 0x204
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P_MEMSET32 = 0x205
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P_MEMSET16 = 0x206
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P_MEMSET8 = 0x207
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P_IC_IALLUIS = 0x300
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P_IC_IALLU = 0x301
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P_IC_IVAU = 0x302
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P_DC_IVAC = 0x303
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P_DC_ISW = 0x304
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P_DC_CSW = 0x305
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P_DC_CISW = 0x306
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P_DC_ZVA = 0x307
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P_DC_CVAC = 0x308
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P_DC_CVAU = 0x309
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P_DC_CIVAC = 0x30a
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P_XZDEC = 0x400
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P_GZDEC = 0x401
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def __init__(self, iface, debug=False):
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self.debug = debug
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self.iface = iface
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def request(self, opcode, *args, reboot=False, signed=False, no_reply=False):
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if len(args) > 6:
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raise ValueError("Too many arguments")
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args = list(args) + [0] * (6 - len(args))
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req = struct.pack("<7Q", opcode, *args)
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if self.debug:
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print("<<<< %08x: %08x %08x %08x %08x %08x %08x"%tuple([opcode] + args))
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reply = self.iface.proxyreq(req, reboot=reboot, no_reply=no_reply)
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if no_reply:
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return
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ret_fmt = "q" if signed else "Q"
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rop, status, retval = struct.unpack("<Qq" + ret_fmt, reply)
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if self.debug:
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print(">>>> %08x: %d %08x"%(rop, status, retval))
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if reboot:
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return
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if rop != opcode:
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raise ProxyCMDError("Reply opcode mismatch: Expected 0x%08x, got 0x%08x"%(opcode,rop))
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if status != self.S_OK:
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if status == self.S_BADCMD:
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raise ProxyRemoteError("Reply error: Bad Command")
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else:
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raise ProxyRemoteError("Reply error: Unknown error (%d)"%status)
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return retval
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def nop(self):
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self.request(self.P_NOP)
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def exit(self):
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self.request(self.P_EXIT)
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def call(self, addr, *args):
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if len(args) > 4:
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raise ValueError("Too many arguments")
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return self.request(self.P_CALL, addr, *args)
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def reboot(self, addr, *args):
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if len(args) > 4:
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raise ValueError("Too many arguments")
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self.request(self.P_CALL, addr, *args, reboot=True)
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def vector(self, addr, *args):
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if len(args) > 4:
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raise ValueError("Too many arguments")
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self.request(self.P_CALL, addr, *args, no_reply=True)
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def get_bootargs(self):
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return self.request(self.P_GET_BOOTARGS)
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def get_base(self):
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return self.request(self.P_GET_BASE)
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def set_baud(self, baudrate):
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self.iface.tty_enable = False
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try:
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self.request(self.P_SET_BAUD, baudrate, 16, 0x005aa5f0)
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finally:
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self.iface.tty_enable = True
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def write64(self, addr, data):
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if addr & 7:
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raise AlignmentError()
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self.request(self.P_WRITE64, addr, data)
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def write32(self, addr, data):
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if addr & 3:
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raise AlignmentError()
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self.request(self.P_WRITE32, addr, data)
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def write16(self, addr, data):
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if addr & 1:
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raise AlignmentError()
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self.request(self.P_WRITE16, addr, data)
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def write8(self, addr, data):
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self.request(self.P_WRITE8, addr, data)
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def read64(self, addr):
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if addr & 7:
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raise AlignmentError()
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return self.request(self.P_READ64, addr)
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def read32(self, addr):
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if addr & 3:
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raise AlignmentError()
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return self.request(self.P_READ32, addr)
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def read16(self, addr):
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if addr & 1:
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raise AlignmentError()
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return self.request(self.P_READ16, addr)
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def read8(self, addr):
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return self.request(self.P_READ8, addr)
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def set64(self, addr, data):
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if addr & 7:
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raise AlignmentError()
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self.request(self.P_SET64, addr, data)
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def set32(self, addr, data):
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if addr & 3:
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raise AlignmentError()
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self.request(self.P_SET32, addr, data)
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def set16(self, addr, data):
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if addr & 1:
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raise AlignmentError()
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self.request(self.P_SET16, addr, data)
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def set8(self, addr, data):
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self.request(self.P_SET8, addr, data)
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def clear64(self, addr, data):
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if addr & 7:
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raise AlignmentError()
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self.request(self.P_CLEAR64, addr, data)
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def clear32(self, addr, data):
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if addr & 3:
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raise AlignmentError()
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self.request(self.P_CLEAR32, addr, data)
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def clear16(self, addr, data):
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if addr & 1:
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raise AlignmentError()
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self.request(self.P_CLEAR16, addr, data)
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def clear8(self, addr, data):
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self.request(self.P_CLEAR8, addr, data)
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def mask64(self, addr, clear, set):
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if addr & 7:
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raise AlignmentError()
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self.request(self.P_MASK64, addr, clear, set)
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def mask32(self, addr, clear, set):
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if addr & 3:
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raise AlignmentError()
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self.request(self.P_MASK32, addr, clear, set)
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def mask16(self, addr, clear, set):
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if addr & 1:
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raise AlignmentError()
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self.request(self.P_MASK16, addr, clear, set)
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def mask8(self, addr, clear, set):
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self.request(self.P_MASK8, addr, clear, set)
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def memcpy64(self, dst, src, size):
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if src & 7 or dst & 7:
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raise AlignmentError()
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self.request(self.P_MEMCPY64, dst, src, size)
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def memcpy32(self, dst, src, size):
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if src & 3 or dst & 3:
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raise AlignmentError()
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self.request(self.P_MEMCPY32, dst, src, size)
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def memcpy16(self, dst, src, size):
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if src & 1 or dst & 1:
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raise AlignmentError()
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self.request(self.P_MEMCPY16, dst, src, size)
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def memcpy8(self, dst, src, size):
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self.request(self.P_MEMCPY8, dst, src, size)
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def memset64(self, dst, src, size):
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if dst & 7:
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raise AlignmentError()
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self.request(self.P_MEMSET64, dst, src, size)
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def memset32(self, dst, src, size):
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if dst & 3:
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raise AlignmentError()
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self.request(self.P_MEMSET32, dst, src, size)
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def memset16(self, dst, src, size):
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if dst & 1:
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raise AlignmentError()
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self.request(self.P_MEMSET16, dst, src, size)
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def memset8(self, dst, src, size):
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self.request(self.P_MEMSET8, dst, src, size)
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def ic_ialluis(self):
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self.request(self.P_IC_IALLUIS)
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def ic_iallu(self):
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self.request(self.P_IC_IALLU)
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def ic_ivau(self, addr, size):
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self.request(self.P_IC_IVAU, addr, size)
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def ic_ivac(self, addr, size):
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self.request(self.P_IC_IVAC, addr, size)
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def dc_isw(self, sw):
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self.request(self.P_DC_ISW, sw)
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def dc_csw(self, sw):
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self.request(self.P_DC_CSW, sw)
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def dc_cisw(self, sw):
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self.request(self.P_DC_CISW, sw)
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def dc_zva(self, addr, size):
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self.request(self.P_DC_ZVA, addr, size)
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def dc_cvac(self, addr, size):
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self.request(self.P_DC_CVAC, addr, size)
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def dc_cvau(self, addr, size):
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self.request(self.P_DC_CVAU, addr, size)
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def dc_civac(self, addr, size):
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self.request(self.P_DC_CIVAC, addr, size)
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def xzdec(self, inbuf, insize, outbuf=0, outsize=0):
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return self.request(self.P_XZDEC, inbuf, insize, outbuf,
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outsize, signed=True)
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def gzdec(self, inbuf, insize, outbuf, outsize):
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return self.request(self.P_GZDEC, inbuf, insize, outbuf,
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outsize, signed=True)
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if __name__ == "__main__":
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import serial
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uartdev = os.environ.get("M1N1DEVICE", "/dev/ttyUSB0")
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usbuart = serial.Serial(uartdev, 115200)
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|
uartif = UartInterface(usbuart, debug=True)
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|
print("Sending NOP...", end=' ')
|
|
uartif.nop()
|
|
print("OK")
|
|
proxy = M1N1Proxy(uartif, debug=True)
|
|
print("Sending Proxy NOP...", end=' ')
|
|
proxy.nop()
|
|
print("OK")
|
|
print("Boot args: 0x%x" % proxy.get_bootargs())
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