mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-10 09:44:13 +00:00
b2a479f1bf
It seems we missed this config all along. Signed-off-by: Hector Martin <marcan@marcan.st>
151 lines
4.3 KiB
C
151 lines
4.3 KiB
C
/* SPDX-License-Identifier: MIT */
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#include "chickens.h"
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#include "cpu_regs.h"
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#include "uart.h"
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#include "utils.h"
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/* Part IDs in MIDR_EL1 */
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#define MIDR_PART_T8181_ICESTORM 0x20
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#define MIDR_PART_T8181_FIRESTORM 0x21
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#define MIDR_PART_T8103_ICESTORM 0x22
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#define MIDR_PART_T8103_FIRESTORM 0x23
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#define MIDR_PART_T6000_ICESTORM 0x24
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#define MIDR_PART_T6000_FIRESTORM 0x25
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#define MIDR_PART_T6001_ICESTORM 0x28
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#define MIDR_PART_T6001_FIRESTORM 0x29
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#define MIDR_PART_T8110_BLIZZARD 0x30
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#define MIDR_PART_T8110_AVALANCHE 0x31
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#define MIDR_PART_T8112_BLIZZARD 0x32
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#define MIDR_PART_T8112_AVALANCHE 0x33
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#define MIDR_PART_T6020_BLIZZARD 0x34
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#define MIDR_PART_T6020_AVALANCHE 0x35
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#define MIDR_PART_T6021_BLIZZARD 0x38
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#define MIDR_PART_T6021_AVALANCHE 0x39
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#define MIDR_REV_LOW GENMASK(3, 0)
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#define MIDR_PART GENMASK(15, 4)
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#define MIDR_REV_HIGH GENMASK(23, 20)
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void init_m1_icestorm(void);
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void init_t8103_firestorm(int rev);
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void init_t6000_firestorm(int rev);
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void init_t6001_firestorm(int rev);
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void init_t8112_blizzard(void);
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void init_t8112_avalanche(int rev);
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void init_t6020_blizzard(void);
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void init_t6020_avalanche(int rev);
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void init_t6021_blizzard(void);
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void init_t6021_avalanche(int rev);
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const char *init_cpu(void)
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{
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const char *cpu = "Unknown";
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msr(OSLAR_EL1, 0);
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/* This is performed unconditionally on all cores (necessary?) */
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if (is_ecore())
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reg_set(SYS_IMP_APL_EHID4, HID4_DISABLE_DC_MVA | HID4_DISABLE_DC_SW_L2_OPS);
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else
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reg_set(SYS_IMP_APL_HID4, HID4_DISABLE_DC_MVA | HID4_DISABLE_DC_SW_L2_OPS);
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/* Enable NEX powergating, the reset cycles might be overriden by chickens */
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if (!is_ecore()) {
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reg_mask(SYS_IMP_APL_HID13, HID13_RESET_CYCLES_MASK, HID13_RESET_CYCLES(12));
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reg_set(SYS_IMP_APL_HID14, HID14_ENABLE_NEX_POWER_GATING);
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}
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uint64_t midr = mrs(MIDR_EL1);
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int part = FIELD_GET(MIDR_PART, midr);
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int rev = (FIELD_GET(MIDR_REV_HIGH, midr) << 4) | FIELD_GET(MIDR_REV_LOW, midr);
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printf(" CPU part: 0x%x rev: 0x%x\n", part, rev);
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switch (part) {
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case MIDR_PART_T8103_FIRESTORM:
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cpu = "M1 Firestorm";
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init_t8103_firestorm(rev);
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break;
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case MIDR_PART_T6000_FIRESTORM:
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cpu = "M1 Pro Firestorm";
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init_t6000_firestorm(rev);
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break;
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case MIDR_PART_T6001_FIRESTORM:
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cpu = "M1 Max Firestorm";
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init_t6001_firestorm(rev);
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break;
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case MIDR_PART_T8103_ICESTORM:
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cpu = "M1 Icestorm";
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init_m1_icestorm();
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break;
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case MIDR_PART_T6000_ICESTORM:
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cpu = "M1 Pro Icestorm";
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init_m1_icestorm();
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break;
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case MIDR_PART_T6001_ICESTORM:
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cpu = "M1 Max Icestorm";
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init_m1_icestorm();
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break;
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case MIDR_PART_T8112_AVALANCHE:
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cpu = "M2 Avalanche";
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init_t8112_avalanche(rev);
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break;
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case MIDR_PART_T8112_BLIZZARD:
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cpu = "M2 Blizzard";
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init_t8112_blizzard();
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break;
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case MIDR_PART_T6020_AVALANCHE:
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cpu = "M2 Pro Avalanche";
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init_t6020_avalanche(rev);
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break;
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case MIDR_PART_T6020_BLIZZARD:
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cpu = "M2 Pro Blizzard";
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init_t6020_blizzard();
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break;
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case MIDR_PART_T6021_AVALANCHE:
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cpu = "M2 Max Avalanche";
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init_t6021_avalanche(rev);
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break;
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case MIDR_PART_T6021_BLIZZARD:
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cpu = "M2 Max Blizzard";
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init_t6021_blizzard();
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break;
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default:
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uart_puts(" Unknown CPU type");
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break;
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}
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int core = mrs(MPIDR_EL1) & 0xff;
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// Unknown, related to SMP?
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msr(s3_4_c15_c5_0, core);
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msr(SYS_IMP_APL_AMX_CTL_EL1, 0x100);
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// Enable IRQs (at least necessary on t600x)
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msr(s3_4_c15_c10_4, 0);
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sysop("isb");
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/* Unmask external IRQs, set WFI mode to up (2) */
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reg_mask(SYS_IMP_APL_CYC_OVRD,
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CYC_OVRD_FIQ_MODE_MASK | CYC_OVRD_IRQ_MODE_MASK | CYC_OVRD_WFI_MODE_MASK,
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CYC_OVRD_FIQ_MODE(0) | CYC_OVRD_IRQ_MODE(0) | CYC_OVRD_WFI_MODE(2));
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/* Enable branch prediction state retention across ACC sleep */
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reg_mask(SYS_IMP_APL_ACC_CFG, ACC_CFG_BP_SLEEP_MASK, ACC_CFG_BP_SLEEP(3));
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return cpu;
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}
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