mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-23 07:03:08 +00:00
694 lines
22 KiB
Python
694 lines
22 KiB
Python
#!/usr/bin/env python3
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# SPDX-License-Identifier: MIT
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import sys, traceback, struct, array, bisect, os
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from construct import *
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from asm import ARMAsm
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from tgtypes import *
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from proxy import IODEV, START, EVENT, EXC, EXC_RET, ExcInfo
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from utils import *
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from sysreg import *
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from macho import MachO
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from adt import load_adt
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import xnutools
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import shell
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PAC_MASK = 0xfffff00000000000
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class MMIOTraceFlags(Register32):
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WIDTH = 2, 0
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WRITE = 3
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EvtMMIOTrace = Struct(
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"flags" / RegAdapter(MMIOTraceFlags),
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"reserved" / Int32ul,
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"pc" / Hex(Int64ul),
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"addr" / Hex(Int64ul),
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"data" / Hex(Int64ul),
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)
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class HOOK(IntEnum):
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VM = 1
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VMProxyHookData = Struct(
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"flags" / RegAdapter(MMIOTraceFlags),
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"id" / Int32ul,
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"addr" / Hex(Int64ul),
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"data" / Hex(Int64ul),
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)
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class HV:
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PTE_VALID = 1 << 0
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PTE_MEMATTR_UNCHANGED = 0b1111 << 2
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PTE_S2AP_RW = 0b11 << 6
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PTE_SH_NS = 0b11 << 8
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PTE_ACCESS = 1 << 10
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PTE_ATTRIBUTES = PTE_ACCESS | PTE_SH_NS | PTE_S2AP_RW | PTE_MEMATTR_UNCHANGED
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SPTE_TRACE_READ = 1 << 63
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SPTE_TRACE_WRITE = 1 << 62
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SPTE_SYNC_TRACE = 1 << 61
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SPTE_MAP = 0 << 50
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SPTE_HOOK = 1 << 50
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SPTE_PROXY_HOOK_R = 2 << 50
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SPTE_PROXY_HOOK_W = 3 << 50
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SPTE_PROXY_HOOK_RW = 4 << 50
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MSR_REDIRECTS = {
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SCTLR_EL1: SCTLR_EL12,
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TTBR0_EL1: TTBR0_EL12,
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TTBR1_EL1: TTBR1_EL12,
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TCR_EL1: TCR_EL12,
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ESR_EL1: ESR_EL12,
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FAR_EL1: FAR_EL12,
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AFSR0_EL1: AFSR0_EL12,
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AFSR1_EL1: AFSR1_EL12,
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MAIR_EL1: MAIR_EL12,
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AMAIR_EL1: AMAIR_EL12,
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CONTEXTIDR_EL1: CONTEXTIDR_EL12,
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ACTLR_EL1: ACTLR_EL12,
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AMX_CTL_EL1: AMX_CTL_EL12,
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SPRR_CONFIG_EL1: SPRR_CONFIG_EL12,
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SPRR_PERM_EL1: SPRR_PERM_EL12,
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SPRR_PERM_EL0: SPRR_PERM_EL02,
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SPRR_UNK1_EL1: SPRR_UNK1_EL12,
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SPRR_UMASK_EL1: SPRR_UMASK_EL12,
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APCTL_EL1: APCTL_EL12,
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APSTS_EL1: APSTS_EL12,
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KERNELKEYLO_EL1: KERNELKEYLO_EL12,
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KERNELKEYHI_EL1: KERNELKEYHI_EL12,
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GXF_CONFIG_EL1: GXF_CONFIG_EL12,
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}
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def __init__(self, iface, proxy, utils):
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self.iface = iface
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self.p = proxy
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self.u = utils
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self.vbar_el1 = None
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self.want_vbar = None
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self.vectors = [None]
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self.step = False
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self.sym_offset = 0
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self.symbols = []
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self.sysreg = {}
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self.vm_hooks = []
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def unmap(self, ipa, size):
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assert self.p.hv_map(ipa, 0, size, 0) >= 0
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def map_hw(self, ipa, pa, size):
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assert self.p.hv_map(ipa, pa | self.PTE_ATTRIBUTES | self.PTE_VALID, size, 1) >= 0
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def map_sw(self, ipa, pa, size):
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assert self.p.hv_map(ipa, pa | self.SPTE_MAP, size, 1) >= 0
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def map_hook(self, ipa, size, read=None, write=None, **kwargs):
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if read is not None:
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if write is not None:
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t = self.SPTE_PROXY_HOOK_RW
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else:
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t = self.SPTE_PROXY_HOOK_R
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elif write is not None:
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t = self.SPTE_PROXY_HOOK_W
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else:
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assert False
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index = len(self.vm_hooks)
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self.vm_hooks.append((read, write, ipa, kwargs))
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assert self.p.hv_map(ipa, (index << 2) | t, size, 1) >= 0
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def addr(self, addr):
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unslid_addr = addr + self.sym_offset
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if addr < self.tba.virt_base or unslid_addr < self.macho.vmin:
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return f"0x{addr:x}"
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saddr, name = self.sym(addr)
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if name is None:
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return f"0x{addr:x} (0x{unslid_addr:x})"
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return f"0x{addr:x} ({name}+0x{unslid_addr - saddr:x})"
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def sym(self, addr):
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unslid_addr = addr + self.sym_offset
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if addr < self.tba.virt_base or unslid_addr < self.macho.vmin:
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return None, None
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idx = bisect.bisect_left(self.symbols, (unslid_addr + 1, "")) - 1
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if idx < 0 or idx >= len(self.symbols):
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return f"0x{addr:x} (0x{unslid_addr:x})"
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return self.symbols[idx]
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def handle_mmiotrace(self, data):
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evt = EvtMMIOTrace.parse(data)
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if evt.flags.WRITE:
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t = "W"
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else:
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t = "R"
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print(f"[0x{evt.pc:016x}] MMIO: {t} 0x{evt.addr:x} = 0x{evt.data:x}")
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def handle_vm_hook(self, ctx):
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data = self.iface.readstruct(ctx.data, VMProxyHookData)
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rfunc, wfunc, base, kwargs = self.vm_hooks[data.id]
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if data.flags.WRITE:
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wfunc(base, data.addr - base, data.data, 1 << data.flags.WIDTH, **kwargs)
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else:
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val = rfunc(base, data.addr - base, 1 << data.flags.WIDTH, **kwargs)
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self.p.write64(ctx.data + 16, val)
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return True
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def handle_msr(self, ctx, iss=None):
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if iss is None:
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iss = ctx.esr.ISS
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iss = ESR_ISS_MSR(iss)
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enc = iss.Op0, iss.Op1, iss.CRn, iss.CRm, iss.Op2
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if enc in sysreg_rev:
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name = sysreg_rev[enc]
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else:
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name = f"s{iss.Op0}_{iss.Op1}_c{iss.CRn}_c{iss.CRm}_{iss.Op2}"
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skip = set()
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shadow = {
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#SPRR_CONFIG_EL1,
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#SPRR_PERM_EL0,
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#SPRR_PERM_EL1,
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VMSA_LOCK_EL1,
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#SPRR_UNK1_EL1,
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#SPRR_UNK2_EL1,
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}
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ro = {
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ACC_CFG_EL1,
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CYC_OVRD_EL1,
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ACC_OVRD_EL1,
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}
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value = 0
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if enc in shadow:
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if iss.DIR == MSR_DIR.READ:
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value = self.sysreg.setdefault(enc, 0)
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print(f"Shadow: mrs x{iss.Rt}, {name} = {value:x}")
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if iss.Rt != 31:
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ctx.regs[iss.Rt] = value
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else:
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if iss.Rt != 31:
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value = ctx.regs[iss.Rt]
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print(f"Shadow: msr {name}, x{iss.Rt} = {value:x}")
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self.sysreg[enc] = value
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elif enc in skip or (enc in ro and iss.DIR == MSR_DIR.WRITE):
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if iss.DIR == MSR_DIR.READ:
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print(f"Skip: mrs x{iss.Rt}, {name} = 0")
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if iss.Rt != 31:
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ctx.regs[iss.Rt] = 0
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else:
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value = ctx.regs[iss.Rt]
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print(f"Skip: msr {name}, x{iss.Rt} = {value:x}")
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else:
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if iss.DIR == MSR_DIR.READ:
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print(f"Pass: mrs x{iss.Rt}, {name}", end=" ")
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sys.stdout.flush()
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value = self.u.mrs(self.MSR_REDIRECTS.get(enc, enc))
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print(f"= {value:x}")
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if iss.Rt != 31:
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ctx.regs[iss.Rt] = value
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else:
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if iss.Rt != 31:
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value = ctx.regs[iss.Rt]
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print(f"Pass: msr {name}, x{iss.Rt} = {value:x}", end=" ")
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sys.stdout.flush()
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self.u.msr(self.MSR_REDIRECTS.get(enc, enc), value, call=self.p.gl2_call)
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print("(OK)")
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ctx.elr += 4
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self.patch_exception_handling()
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return True
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def handle_impdef(self, ctx):
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if ctx.esr.ISS == 0x20:
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return self.handle_msr(ctx, self.u.mrs(AFSR1_EL1))
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start = ctx.elr_phys
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code = struct.unpack("<I", self.iface.readmem(ctx.elr_phys, 4))
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c = ARMAsm(".inst " + ",".join(str(i) for i in code), ctx.elr_phys)
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insn = "; ".join(c.disassemble())
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print(f"IMPDEF exception on: {insn}")
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return False
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def handle_hvc(self, ctx):
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idx = ctx.esr.ISS
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if idx == 0:
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return False
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vector, target = self.vectors[idx]
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if target is None:
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print(f"EL1: Exception #{vector} with no target")
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target = 0
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ok = False
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else:
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ctx.elr = target
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ctx.elr_phys = self.p.hv_translate(target, False, False)
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ok = True
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if (vector & 3) == EXC.SYNC:
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spsr = SPSR(self.u.mrs(SPSR_EL12))
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esr = ESR(self.u.mrs(ESR_EL12))
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elr = self.u.mrs(ELR_EL12)
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elr_phys = self.p.hv_translate(elr, False, False)
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sp_el1 = self.u.mrs(SP_EL1)
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sp_el0 = self.u.mrs(SP_EL0)
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far = None
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if esr.EC == ESR_EC.DABORT or esr.EC == ESR_EC.IABORT:
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far = self.u.mrs(FAR_EL12)
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if self.sym(elr)[1] != "com.apple.kernel:_panic_trap_to_debugger":
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print("Page fault")
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return ok
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print(f"EL1: Exception #{vector} ({esr.EC!s}) to {self.addr(target)} from {spsr.M.name}")
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print(f" ELR={self.addr(elr)} (0x{elr_phys:x})")
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print(f" SP_EL1=0x{sp_el1:x} SP_EL0=0x{sp_el0:x}")
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if far is not None:
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print(f" FAR={self.addr(far)}")
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if elr_phys:
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self.u.disassemble_at(elr_phys - 4 * 4, 9 * 4, elr_phys)
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if self.sym(elr)[1] == "com.apple.kernel:_panic_trap_to_debugger":
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print("Panic! Trying to decode panic...")
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try:
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self.decode_panic_call()
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except:
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print("Error decoding panic.")
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try:
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self.bt()
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except:
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pass
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return False
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if esr.EC == ESR_EC.UNKNOWN:
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instr = self.p.read32(elr_phys)
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if instr == 0xe7ffdeff:
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print("Debugger break! Trying to decode panic...")
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try:
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self.decode_dbg_panic()
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except:
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print("Error decoding panic.")
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try:
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self.bt()
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except:
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pass
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return False
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return False
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else:
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elr = self.u.mrs(ELR_EL12)
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print(f"Guest: {str(EXC(vector & 3))} at {self.addr(elr)}")
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return ok
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def handle_sync(self, ctx):
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if ctx.esr.EC == ESR_EC.MSR:
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return self.handle_msr(ctx)
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if ctx.esr.EC == ESR_EC.IMPDEF:
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return self.handle_impdef(ctx)
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if ctx.esr.EC == ESR_EC.HVC:
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return self.handle_hvc(ctx)
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def handle_exception(self, reason, code, info):
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info_data = self.iface.readmem(info, ExcInfo.sizeof())
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self.ctx = ctx = ExcInfo.parse(info_data)
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handled = False
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try:
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if reason == START.EXCEPTION_LOWER:
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if code == EXC.SYNC:
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handled = self.handle_sync(ctx)
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elif code == EXC.FIQ:
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self.u.msr(CNTV_CTL_EL0, 0)
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self.u.print_exception(code, ctx)
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handled = True
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elif reason == START.HV_HOOK:
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code = HOOK(code)
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if code == HOOK.VM:
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handled = self.handle_vm_hook(ctx)
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except Exception as e:
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print(f"Python exception while handling guest exception:")
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traceback.print_exc()
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if handled:
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ret = EXC_RET.HANDLED
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else:
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print(f"Guest exception: {reason.name}/{code.name}")
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self.u.print_exception(code, ctx)
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locals = {
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"hv": self,
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"iface": self.iface,
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"p": self.p,
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"u": self.u,
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}
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for attr in dir(self):
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a = getattr(self, attr)
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if callable(a):
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locals[attr] = getattr(self, attr)
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ret = shell.run_shell(locals, "Entering debug shell", "Returning from exception")
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if ret is None:
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ret = EXC_RET.EXIT_GUEST
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new_info = ExcInfo.build(self.ctx)
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if new_info != info_data:
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self.iface.writemem(info, new_info)
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if ret == EXC_RET.HANDLED and self.step:
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ret = EXC_RET.STEP
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self.p.exit(ret)
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def skip(self):
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self.ctx.elr += 4
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raise shell.ExitConsole(EXC_RET.HANDLED)
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def cont(self):
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raise shell.ExitConsole(EXC_RET.HANDLED)
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def exit(self):
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raise shell.ExitConsole(EXC_RET.EXIT_GUEST)
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def hvc(self, arg):
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assert 0 <= arg <= 0xffff
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return 0xd4000002 | (arg << 5)
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def decode_dbg_panic(self):
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xnutools.decode_debugger_state(self.u, self.ctx)
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def decode_panic_call(self):
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xnutools.decode_panic_call(self.u, self.ctx)
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def bt(self, frame=None, lr=None):
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if frame is None:
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frame = self.ctx.regs[29]
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if lr is None:
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lr = self.ctx.regs[30] | PAC_MASK
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print("Stack trace:")
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while frame:
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print(f" - {self.addr(lr - 4)}")
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lrp = self.p.hv_translate(frame + 8)
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fpp = self.p.hv_translate(frame)
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if not fpp:
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break
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lr = self.p.read64(lrp) | PAC_MASK
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frame = self.p.read64(fpp)
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def patch_exception_handling(self):
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if self.want_vbar is not None:
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vbar = self.want_vbar
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else:
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vbar = self.u.mrs(VBAR_EL12)
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if vbar == self.vbar_el1:
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return
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if vbar == 0:
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return
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if self.u.mrs(SCTLR_EL12) & 1:
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vbar_phys = self.p.hv_translate(vbar, False, False)
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if vbar_phys == 0:
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print(f"VBAR vaddr 0x{vbar:x} translation failed!")
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if self.vbar_el1 is not None:
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self.want_vbar = vbar
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self.u.msr(VBAR_EL12, self.vbar_el1)
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return
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else:
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if vbar & (1 << 63):
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print(f"VBAR vaddr 0x{vbar:x} without translation enabled")
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if self.vbar_el1 is not None:
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self.want_vbar = vbar
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self.u.msr(VBAR_EL12, self.vbar_el1)
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return
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vbar_phys = vbar
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if self.want_vbar is not None:
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self.want_vbar = None
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self.u.msr(VBAR_EL12, vbar)
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print(f"New VBAR paddr: 0x{vbar_phys:x}")
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#for i in range(16):
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for i in [0, 3, 4, 7, 8, 11, 12, 15]:
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idx = 0
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addr = vbar_phys + 0x80 * i
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orig = self.p.read32(addr)
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if (orig & 0xfc000000) != 0x14000000:
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print(f"Unknown vector #{i}:\n")
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self.u.disassemble_at(addr, 16)
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else:
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idx = len(self.vectors)
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delta = orig & 0x3ffffff
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if delta == 0:
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target = None
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print(f"Vector #{i}: Loop\n")
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else:
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target = (delta << 2) + vbar + 0x80 * i
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print(f"Vector #{i}: 0x{target:x}\n")
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self.vectors.append((i, target))
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self.u.disassemble_at(addr, 16)
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self.p.write32(addr, self.hvc(idx))
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self.p.dc_cvau(vbar_phys, 0x800)
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self.p.ic_ivau(vbar_phys, 0x800)
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self.vbar_el1 = vbar
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def init(self):
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self.adt = load_adt(self.u.get_adt())
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self.iodev = self.p.iodev_whoami()
|
|
self.tba = self.u.ba.copy()
|
|
|
|
print("Initializing hypervisor over iodev %s" % self.iodev)
|
|
self.p.hv_init()
|
|
|
|
self.iface.set_handler(START.EXCEPTION_LOWER, EXC.SYNC, self.handle_exception)
|
|
self.iface.set_handler(START.EXCEPTION_LOWER, EXC.IRQ, self.handle_exception)
|
|
self.iface.set_handler(START.EXCEPTION_LOWER, EXC.FIQ, self.handle_exception)
|
|
self.iface.set_handler(START.EXCEPTION_LOWER, EXC.SERROR, self.handle_exception)
|
|
self.iface.set_handler(START.HV_HOOK, HOOK.VM, self.handle_exception)
|
|
self.iface.set_event_handler(EVENT.MMIOTRACE, self.handle_mmiotrace)
|
|
|
|
self.map_hw(0x2_00000000, 0x2_00000000, 0x5_00000000)
|
|
|
|
hcr = HCR(self.u.mrs(HCR_EL2))
|
|
hcr.TACR = 1
|
|
hcr.TIDCP = 0
|
|
hcr.TVM = 0
|
|
hcr.FMO = 0
|
|
hcr.IMO = 0
|
|
self.u.msr(HCR_EL2, hcr.value)
|
|
|
|
# Trap dangerous things
|
|
hacr = HACR(0)
|
|
#hacr.TRAP_CPU_EXT = 1
|
|
#hacr.TRAP_SPRR = 1
|
|
#hacr.TRAP_GXF = 1
|
|
hacr.TRAP_CTRR = 1
|
|
hacr.TRAP_EHID = 1
|
|
hacr.TRAP_HID = 1
|
|
hacr.TRAP_ACC = 1
|
|
self.u.msr(HACR_EL2, hacr.value)
|
|
|
|
# Enable AMX
|
|
amx_ctl = AMX_CTL(self.u.mrs(AMX_CTL_EL1))
|
|
amx_ctl.EN_EL1 = 1
|
|
self.u.msr(AMX_CTL_EL1, amx_ctl.value)
|
|
|
|
# Set guest AP keys
|
|
self.u.msr(APVMKEYLO_EL2, 0x4E7672476F6E6147)
|
|
self.u.msr(APVMKEYHI_EL2, 0x697665596F755570)
|
|
self.u.msr(APSTS_EL12, 1)
|
|
|
|
#self.p.hv_map_vuart(0x2_35200000, getattr(IODEV, self.iodev.name + "_SEC"))
|
|
|
|
actlr = ACTLR(self.u.mrs(ACTLR_EL12))
|
|
actlr.EnMDSB = 1
|
|
self.u.msr(ACTLR_EL12, actlr.value)
|
|
|
|
self.setup_adt()
|
|
|
|
def setup_adt(self):
|
|
if self.iodev in (IODEV.USB0, IODEV.USB1):
|
|
idx = int(str(self.iodev)[-1])
|
|
for prefix in ("dart-usb%d",
|
|
"atc-phy%d",
|
|
"usb-drd%d",
|
|
"acio%d",
|
|
"apciec%d",
|
|
"dart-apciec%d",
|
|
"apciec%d-piodma"):
|
|
name = prefix % idx
|
|
print(f"Removing ADT node /arm-io/{name}")
|
|
try:
|
|
del self.adt["arm-io"][name]
|
|
except KeyError:
|
|
pass
|
|
|
|
#for cpu in list(self.adt["cpus"]):
|
|
#if cpu.name != "cpu0":
|
|
#print(f"Removing ADT node {cpu._path}")
|
|
#try:
|
|
#del self.adt["cpus"][cpu.name]
|
|
#except KeyError:
|
|
#pass
|
|
|
|
def set_bootargs(self, boot_args):
|
|
if "-v" in boot_args.split():
|
|
self.tba.video.display = 0
|
|
else:
|
|
self.tba.video.display = 1
|
|
print(f"Setting boot arguments to {boot_args!r}")
|
|
self.tba.cmdline = boot_args
|
|
|
|
def load_macho(self, data, symfile=None):
|
|
if isinstance(data, str):
|
|
data = open(data, "rb")
|
|
|
|
self.macho = macho = MachO(data)
|
|
symbols = None
|
|
if symfile is not None:
|
|
if isinstance(symfile, str):
|
|
symfile = open(symfile, "rb")
|
|
syms = MachO(symfile)
|
|
macho.add_symbols("com.apple.kernel", syms)
|
|
|
|
self.symbols = [(v, k) for k, v in macho.symbols.items()]
|
|
self.symbols.sort()
|
|
|
|
def load_hook(data, segname, size, fileoff, dest):
|
|
if segname != "__TEXT_EXEC":
|
|
return data
|
|
|
|
print(f"Patching segment {segname}...")
|
|
|
|
a = array.array("I", data)
|
|
|
|
output = []
|
|
|
|
p = 0
|
|
while (p := data.find(b"\x20\x00", p)) != -1:
|
|
if (p & 3) != 2:
|
|
p += 1
|
|
continue
|
|
|
|
opcode = a[p // 4]
|
|
inst = self.hvc((opcode & 0xffff))
|
|
off = fileoff + (p & ~3)
|
|
if off >= 0xbfcfc0:
|
|
print(f" 0x{off:x}: 0x{opcode:04x} -> hvc 0x{opcode:x} (0x{inst:x})")
|
|
a[p // 4] = inst
|
|
p += 4
|
|
|
|
print("Done.")
|
|
return a.tobytes()
|
|
|
|
#image = macho.prepare_image(load_hook)
|
|
image = macho.prepare_image()
|
|
sepfw_start, sepfw_length = self.u.adt["chosen"]["memory-map"].SEPFW
|
|
tc_start, tc_size = self.u.adt["chosen"]["memory-map"].TrustCache
|
|
|
|
image_size = align(len(image))
|
|
sepfw_off = image_size
|
|
image_size += align(sepfw_length)
|
|
self.bootargs_off = image_size
|
|
bootargs_size = 0x4000
|
|
image_size += bootargs_size
|
|
|
|
print(f"Total region size: 0x{image_size:x} bytes")
|
|
|
|
self.phys_base = phys_base = guest_base = self.u.heap_top
|
|
guest_base += 16 << 20 # ensure guest starts within a 16MB aligned region of mapped RAM
|
|
adt_base = guest_base
|
|
guest_base += align(self.u.ba.devtree_size)
|
|
tc_base = guest_base
|
|
guest_base += align(tc_size)
|
|
self.guest_base = guest_base
|
|
mem_top = self.u.ba.phys_base + self.u.ba.mem_size
|
|
mem_size = mem_top - phys_base
|
|
|
|
print(f"Physical memory: 0x{phys_base:x} .. 0x{mem_top:x}")
|
|
print(f"Guest region start: 0x{guest_base:x}")
|
|
|
|
self.entry = macho.entry - macho.vmin + guest_base
|
|
|
|
print(f"Mapping guest physical memory...")
|
|
self.map_hw(phys_base, phys_base, self.u.ba.mem_size_actual - phys_base + 0x800000000)
|
|
|
|
print(f"Loading kernel image (0x{len(image):x} bytes)...")
|
|
self.u.compressed_writemem(guest_base, image, True)
|
|
self.p.dc_cvau(guest_base, len(image))
|
|
self.p.ic_ivau(guest_base, len(image))
|
|
|
|
print(f"Copying SEPFW (0x{sepfw_length:x} bytes)...")
|
|
self.p.memcpy8(guest_base + sepfw_off, sepfw_start, sepfw_length)
|
|
|
|
print(f"Copying TrustCache (0x{tc_size:x} bytes)...")
|
|
self.p.memcpy8(tc_base, tc_start, tc_size)
|
|
|
|
print(f"Adjusting addresses in ADT...")
|
|
self.adt["chosen"]["memory-map"].SEPFW = (guest_base + sepfw_off, sepfw_length)
|
|
self.adt["chosen"]["memory-map"].TrustCache = (tc_base, tc_size)
|
|
self.adt["chosen"]["memory-map"].DeviceTree = (adt_base, align(self.u.ba.devtree_size))
|
|
self.adt["chosen"]["memory-map"].BootArgs = (guest_base + self.bootargs_off, bootargs_size)
|
|
|
|
adt_blob = self.adt.build()
|
|
print(f"Uploading ADT (0x{len(adt_blob):x} bytes)...")
|
|
self.iface.writemem(adt_base, adt_blob)
|
|
|
|
print(f"Setting up bootargs at 0x{guest_base + self.bootargs_off:x}...")
|
|
|
|
self.tba.mem_size = mem_size
|
|
self.tba.phys_base = phys_base
|
|
self.tba.virt_base = 0xfffffe0010000000 + (phys_base & (32 * 1024 * 1024 - 1))
|
|
self.tba.devtree = adt_base - phys_base + self.tba.virt_base
|
|
self.tba.top_of_kernel_data = guest_base + image_size
|
|
|
|
self.sym_offset = macho.vmin - guest_base + self.tba.phys_base - self.tba.virt_base
|
|
|
|
self.iface.writemem(guest_base + self.bootargs_off, BootArgs.build(self.tba))
|
|
|
|
def start(self):
|
|
print(f"Disabling other iodevs...")
|
|
for iodev in IODEV:
|
|
if iodev != self.iodev:
|
|
print(f" - {iodev!s}")
|
|
self.p.iodev_set_usage(iodev, 0)
|
|
|
|
print(f"Shutting down framebuffer...")
|
|
self.p.fb_shutdown()
|
|
|
|
print(f"Enabling SPRR...")
|
|
self.u.msr(SPRR_CONFIG_EL1, 1)
|
|
|
|
print(f"Enabling GXF...")
|
|
self.u.msr(GXF_CONFIG_EL1, 1)
|
|
|
|
print(f"Jumping to entrypoint at 0x{self.entry:x}")
|
|
|
|
self.iface.dev.timeout = None
|
|
|
|
# Does not return
|
|
self.p.hv_start(self.entry, self.guest_base + self.bootargs_off)
|