mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-23 07:03:08 +00:00
247 lines
5.2 KiB
Python
247 lines
5.2 KiB
Python
#!/usr/bin/env python3
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# SPDX-License-Identifier: MIT
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import json, os
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from enum import IntEnum
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from utils import Register64, Register32
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def load_registers():
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for fname in ["arm_regs.json", "apple_regs.json"]:
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data = json.load(open(os.path.join(os.path.dirname(__file__), "..", "tools", fname)))
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for reg in data:
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yield reg["name"], tuple(reg["enc"])
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sysreg_fwd = dict(load_registers())
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sysreg_rev = {v: k for k, v in sysreg_fwd.items()}
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globals().update(sysreg_fwd)
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def sysreg_name(enc):
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if enc in sysreg_rev:
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return sysreg_rev[enc]
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return f"s{enc[0]}_{enc[1]}_c{enc[2]}_c{enc[3]}_{enc[4]}"
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class ESR_EC(IntEnum):
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UNKNOWN = 0b000000
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WFI = 0b000001
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FP_TRAP = 0b000111
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PAUTH_TRAP = 0b001000
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LS64 = 0b001010
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BTI = 0b001101
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ILLEGAL = 0b001110
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SVC = 0b010101
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HVC = 0b010110
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SMC = 0b010111
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MSR = 0b011000
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SVE = 0b011001
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PAUTH_FAIL = 0b011100
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IABORT_LOWER = 0b100000
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IABORT = 0b100001
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PC_ALIGN = 0b100010
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DABORT_LOWER = 0b100100
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DABORT = 0b100101
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SP_ALIGN = 0b100110
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FP_EXC = 0b101100
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SERROR = 0b101111
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BKPT_LOWER = 0b110000
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BKPT = 0b110001
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SSTEP_LOWER = 0b110010
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SSTEP = 0b110011
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WATCH_LOWER = 0b110100
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WATCH = 0b110101
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BRK = 0b111100
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IMPDEF = 0b111111
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class MSR_DIR(IntEnum):
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WRITE = 0
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READ = 1
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class ESR_ISS_MSR(Register32):
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Op0 = 21, 20
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Op2 = 19, 17
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Op1 = 16, 14
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CRn = 13, 10
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Rt = 9, 5
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CRm = 4, 1
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DIR = 0, 0, MSR_DIR
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class DABORT_DFSC(IntEnum):
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ASIZE_L0 = 0b000000
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ASIZE_L1 = 0b000001
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ASIZE_L2 = 0b000010
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ASIZE_L3 = 0b000011
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XLAT_L0 = 0b000100
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XLAT_L1 = 0b000101
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XLAT_L2 = 0b000110
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XLAT_L3 = 0b000111
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AF_L0 = 0b001000
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AF_L1 = 0b001001
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AF_L2 = 0b001010
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AF_L3 = 0b001011
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PERM_L0 = 0b001100
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PERM_L1 = 0b001101
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PERM_L2 = 0b001110
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PERM_L3 = 0b001111
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EABORT = 0b010000
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TAG_CHECK = 0b010001
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PT_EABORT_Lm1 = 0b010011
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PT_EABORT_L0 = 0b010100
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PT_EABORT_L1 = 0b010101
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PT_EABORT_L2 = 0b010110
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PT_EABORT_L3 = 0b010111
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ECC_ERROR = 0b011000
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PT_ECC_ERROR_Lm1 = 0b011011
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PT_ECC_ERROR_L0 = 0b011100
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PT_ECC_ERROR_L1 = 0b011101
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PT_ECC_ERROR_L2 = 0b011110
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PT_ECC_ERROR_L3 = 0b011111
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ALIGN = 0b100001
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ASIZE_Lm1 = 0b101001
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XLAT_Lm1 = 0b101011
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TLB_CONFLICT = 0b110000
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UNSUPP_ATOMIC = 0b110001
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IMPDEF_LOCKDOWN = 0b110100
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IMPDEF_ATOMIC = 0b110101
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class ESR_ISS_DABORT(Register32):
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ISV = 24
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SAS = 23, 22
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SSE = 21
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SRT = 20, 16
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SF = 15
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AR = 14
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VNCR = 13
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SET = 12, 11
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LSR = 12, 11
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FnV = 10
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EA = 9
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CM = 8
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S1PTR = 7
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WnR = 6
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DFSC = 5, 0, DABORT_DFSC
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class ESR(Register64):
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ISS2 = 36, 32
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EC = 31, 26, ESR_EC
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IL = 25
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ISS = 24, 0
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class SPSR_M(IntEnum):
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EP0t = 0
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EL1t = 4
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EL1h = 5
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EL2t = 8
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EL2h = 9
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class SPSR(Register64):
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N = 31
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Z = 30
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C = 29
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V = 28
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TCO = 25
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DIT = 24
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UAO = 23
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PAN = 22
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SS = 21
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IL = 20
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SSBS = 12
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BTYPE = 11, 10
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D = 9
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A = 8
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I = 7
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F = 6
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M = 4, 0, SPSR_M
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class ACTLR(Register64):
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EnMDSB = 12
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EnPRSV = 6
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EnAFP = 5
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EnAPFLG = 4
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DisHWP = 3
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EnTSO = 1
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class HCR(Register64):
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TWEDEL = 63, 60
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TWEDEn = 59
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TID5 = 58
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DCT = 57
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ATA = 56
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TTLBOS = 55
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TTLBIS = 54
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EnSCXT = 53
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TOCU = 52
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AMVOFFEN = 51
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TICAB = 50
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TID4 = 49
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FIEN = 47
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FWB = 46
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NV2 = 45
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AT = 44
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NV1 = 43
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NV1 = 43
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NV = 42
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NV = 42
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API = 41
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APK = 40
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MIOCNCE = 38
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TEA = 37
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TERR = 36
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TLOR = 35
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E2H = 34
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ID = 33
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CD = 32
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RW = 31
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TRVM = 30
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HCD = 29
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TDZ = 28
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TGE = 27
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TVM = 26
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TTLB = 25
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TPU = 24
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TPCP = 23
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TPC = 23
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TSW = 22
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TACR = 21
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TIDCP = 20
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TSC = 19
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TID3 = 18
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TID2 = 17
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TID1 = 16
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TID0 = 15
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TWE = 14
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TWI = 13
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DC = 12
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BSU = 11, 10
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FB = 9
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VSE = 8
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VI = 7
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VF = 6
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AMO = 5
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IMO = 4
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FMO = 3
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PTW = 2
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SWIO = 1
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VM = 0
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class HACR(Register64):
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TRAP_CPU_EXT = 0
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TRAP_AIDR = 4
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TRAP_AMX = 10
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TRAP_SPRR = 11
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TRAP_GXF = 13
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TRAP_CTRR = 14
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TRAP_IPI = 16
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TRAP_s3_4_c15_c5z6_x = 18
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TRAP_s3_4_c15_c0z12_5 = 19
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GIC_CNTV = 20
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TRAP_s3_4_c15_c10_4 = 25
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TRAP_SERROR_INFO = 48
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TRAP_EHID = 49
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TRAP_HID = 50
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TRAP_s3_0_c15_c12_1z2 = 51
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TRAP_ACC = 52
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TRAP_PM = 57
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TRAP_UPM = 58
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TRAP_s3_1z7_c15_cx_3 = 59
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class AMX_CTL(Register64):
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EN = 63
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EN_EL1 = 62
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