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https://github.com/AsahiLinux/m1n1
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c45da55256
The UART base has moved from the M2 chips. Everest settings introduce some changes to unknown registers The MCC data has changed as well. There is a drive-by change where I discovered what some of the unknown HID18 bits are and documented them. Signed-off-by: Daniel Berlin <dberlin@dberlin.org>
336 lines
45 KiB
JSON
336 lines
45 KiB
JSON
[
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{"index": 0, "name": "HID0_EL1", "fullname": "Hardware Implementation-Dependent Register 0", "enc": [3, 0, 15, 0, 0 ], "width": 64},
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{"index": 0, "name": "EHID0_EL1", "fullname": "Hardware Implementation-Dependent Register 0 (E-core)", "enc": [3, 0, 15, 0, 1 ], "width": 64},
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{"index": 0, "name": "HID1_EL1", "fullname": "Hardware Implementation-Dependent Register 1", "enc": [3, 0, 15, 1, 0 ], "width": 64},
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{"index": 0, "name": "EHID1_EL1", "fullname": "Hardware Implementation-Dependent Register 1 (E-core)", "enc": [3, 0, 15, 1, 1 ], "width": 64},
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{"index": 0, "name": "HID2_EL1", "fullname": "Hardware Implementation-Dependent Register 2", "enc": [3, 0, 15, 2, 0 ], "width": 64},
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{"index": 0, "name": "EHID2_EL1", "fullname": "Hardware Implementation-Dependent Register 2 (E-core)", "enc": [3, 0, 15, 2, 1 ], "width": 64},
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{"index": 0, "name": "HID3_EL1", "fullname": "Hardware Implementation-Dependent Register 3", "enc": [3, 0, 15, 3, 0 ], "width": 64},
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{"index": 0, "name": "EHID3_EL1", "fullname": "Hardware Implementation-Dependent Register 3 (E-core)", "enc": [3, 0, 15, 3, 1 ], "width": 64},
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{"index": 0, "name": "HID4_EL1", "fullname": "Hardware Implementation-Dependent Register 4", "enc": [3, 0, 15, 4, 0 ], "width": 64},
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{"index": 0, "name": "EHID4_EL1", "fullname": "Hardware Implementation-Dependent Register 4 (E-core)", "enc": [3, 0, 15, 4, 1 ], "width": 64},
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{"index": 0, "name": "HID5_EL1", "fullname": "Hardware Implementation-Dependent Register 5", "enc": [3, 0, 15, 5, 0 ], "width": 64},
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{"index": 0, "name": "EHID5_EL1", "fullname": "Hardware Implementation-Dependent Register 5 (E-core)", "enc": [3, 0, 15, 5, 1 ], "width": 64},
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{"index": 0, "name": "HID6_EL1", "fullname": "Hardware Implementation-Dependent Register 6", "enc": [3, 0, 15, 6, 0 ], "width": 64},
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{"index": 0, "name": "HID7_EL1", "fullname": "Hardware Implementation-Dependent Register 7", "enc": [3, 0, 15, 7, 0 ], "width": 64},
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{"index": 0, "name": "EHID7_EL1", "fullname": "Hardware Implementation-Dependent Register 7 (E-core)", "enc": [3, 0, 15, 7, 1 ], "width": 64},
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{"index": 0, "name": "HID8_EL1", "fullname": "Hardware Implementation-Dependent Register 8", "enc": [3, 0, 15, 8, 0 ], "width": 64},
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{"index": 0, "name": "HID9_EL1", "fullname": "Hardware Implementation-Dependent Register 9", "enc": [3, 0, 15, 9, 0 ], "width": 64},
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{"index": 0, "name": "EHID9_EL1", "fullname": "Hardware Implementation-Dependent Register 9 (E-core)", "enc": [3, 0, 15, 9, 1 ], "width": 64},
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{"index": 0, "name": "HID10_EL1", "fullname": "Hardware Implementation-Dependent Register 10", "enc": [3, 0, 15, 10, 0 ], "width": 64},
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{"index": 0, "name": "EHID10_EL1", "fullname": "Hardware Implementation-Dependent Register 10 (E-core)", "enc": [3, 0, 15, 10, 1 ], "width": 64},
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{"index": 0, "name": "HID11_EL1", "fullname": "Hardware Implementation-Dependent Register 11", "enc": [3, 0, 15, 11, 0 ], "width": 64},
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{"index": 0, "name": "EHID11_EL1", "fullname": "Hardware Implementation-Dependent Register 11 (E-core)", "enc": [3, 0, 15, 11, 1 ], "width": 64},
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{"index": 0, "name": "HID13_EL1", "fullname": "Hardware Implementation-Dependent Register 13", "enc": [3, 0, 15, 14, 0 ], "width": 64},
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{"index": 0, "name": "HID14_EL1", "fullname": "Hardware Implementation-Dependent Register 14", "enc": [3, 0, 15, 15, 0 ], "width": 64},
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{"index": 0, "name": "HID16_EL1", "fullname": "Hardware Implementation-Dependent Register 16", "enc": [3, 0, 15, 15, 2 ], "width": 64},
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{"index": 0, "name": "HID17_EL1", "fullname": "Hardware Implementation-Dependent Register 17", "enc": [3, 0, 15, 15, 5 ], "width": 64},
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{"index": 0, "name": "HID18_EL1", "fullname": "Hardware Implementation-Dependent Register 18", "enc": [3, 0, 15, 11, 2 ], "width": 64},
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{"index": 0, "name": "EHID18_EL1", "fullname": "Hardware Implementation-Dependent Register 18 (E-core)", "enc": [3, 0, 15, 11, 3 ], "width": 64},
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{"index": 0, "name": "EHID20_EL1", "fullname": "Hardware Implementation-Dependent Register 20 (E-core)", "enc": [3, 0, 15, 1, 2 ], "width": 64},
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{"index": 0, "name": "HID21_EL1", "fullname": "Hardware Implementation-Dependent Register 21", "enc": [3, 0, 15, 1, 3 ], "width": 64},
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{"index": 0, "name": "HID26_EL1", "fullname": "Hardware Implementation-Dependent Register 26", "enc": [3, 0, 15, 0, 3 ], "width": 64},
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{"index": 0, "name": "HID27_EL1", "fullname": "Hardware Implementation-Dependent Register 27", "enc": [3, 0, 15, 0, 4 ], "width": 64},
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{"index": 0, "name": "PMCR0_EL1", "fullname": "Performance Monitor Control Register 0", "enc": [3, 1, 15, 0, 0 ], "width": 64,
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"fieldsets": [{"fields": [
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{"name": "PMC0_EN", "msb": 0, "lsb": 0},
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{"name": "PMC1_EN", "msb": 1, "lsb": 1},
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{"name": "PMC2_EN", "msb": 2, "lsb": 2},
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{"name": "PMC3_EN", "msb": 3, "lsb": 3},
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{"name": "PMC4_EN", "msb": 4, "lsb": 4},
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{"name": "PMC5_EN", "msb": 5, "lsb": 5},
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{"name": "PMC6_EN", "msb": 6, "lsb": 6},
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{"name": "PMC7_EN", "msb": 7, "lsb": 7},
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{"name": "IRQ_MODE", "msb": 10, "lsb": 8},
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{"name": "IRQ_ACTIVE", "msb": 11, "lsb": 11},
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{"name": "PMC0_IRQ_EN", "msb": 12, "lsb": 12},
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{"name": "PMC1_IRQ_EN", "msb": 13, "lsb": 13},
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{"name": "PMC2_IRQ_EN", "msb": 14, "lsb": 14},
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{"name": "PMC3_IRQ_EN", "msb": 15, "lsb": 15},
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{"name": "PMC4_IRQ_EN", "msb": 16, "lsb": 16},
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{"name": "PMC5_IRQ_EN", "msb": 17, "lsb": 17},
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{"name": "PMC6_IRQ_EN", "msb": 18, "lsb": 18},
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{"name": "PMC7_IRQ_EN", "msb": 19, "lsb": 19},
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{"name": "DIS_CNT_PMI", "msb": 20, "lsb": 20},
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{"name": "WAIT_ERET", "msb": 22, "lsb": 22},
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{"name": "CNT_GLOBAL_L2C", "msb": 23, "lsb": 23},
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{"name": "USER_EN", "msb": 30, "lsb": 30},
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{"name": "PMC8_EN", "msb": 32, "lsb": 32},
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{"name": "PMC9_EN", "msb": 33, "lsb": 33},
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{"name": "PMC8_IRQ_EN", "msb": 44, "lsb": 44},
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{"name": "PMC9_IRQ_EN", "msb": 45, "lsb": 45}
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]}]},
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{"index": 0, "name": "PMCR1_EL1", "fullname": "Performance Monitor Control Register 1", "enc": [3, 1, 15, 1, 0 ], "width": 64,
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"fieldsets": [{"fields": [
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{"name": "EL0_A32_PMC_0_7", "msb": 7, "lsb": 0},
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{"name": "EL0_A64_PMC_0_7", "msb": 15, "lsb": 8},
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{"name": "EL1_A64_PMC_0_7", "msb": 23, "lsb": 16},
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{"name": "EL3_A64_PMC_0_7", "msb": 31, "lsb": 24},
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{"name": "EL0_A32_PMC_8_9", "msb": 33, "lsb": 32},
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{"name": "EL0_A64_PMC_8_9", "msb": 41, "lsb": 40},
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{"name": "EL1_A64_PMC_8_9", "msb": 49, "lsb": 48},
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{"name": "EL3_A64_PMC_8_9", "msb": 57, "lsb": 56}
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]}]},
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{"index": 0, "name": "PMCR2_EL1", "fullname": "Performance Monitor Control Register 2", "enc": [3, 1, 15, 2, 0 ], "width": 64},
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{"index": 0, "name": "PMCR3_EL1", "fullname": "Performance Monitor Control Register 3", "enc": [3, 1, 15, 3, 0 ], "width": 64},
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{"index": 0, "name": "PMCR4_EL1", "fullname": "Performance Monitor Control Register 4", "enc": [3, 1, 15, 4, 0 ], "width": 64},
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{"index": 0, "name": "PMESR0_EL1", "fullname": "Performance Monitor Event Selection Register 0", "enc": [3, 1, 15, 5, 0 ], "width": 64,
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"fieldsets": [{"fields": [
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{"name": "PMC2_EVENT_SEL", "msb": 7, "lsb": 0},
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{"name": "PMC3_EVENT_SEL", "msb": 15, "lsb": 8},
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{"name": "PMC4_EVENT_SEL", "msb": 23, "lsb": 16},
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{"name": "PMC5_EVENT_SEL", "msb": 31, "lsb": 24}
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]}]},
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{"index": 0, "name": "PMESR1_EL1", "fullname": "Performance Monitor Event Selection Register 1", "enc": [3, 1, 15, 6, 0 ], "width": 64,
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"fieldsets": [{"fields": [
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{"name": "PMC6_EVENT_SEL", "msb": 7, "lsb": 0},
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{"name": "PMC7_EVENT_SEL", "msb": 15, "lsb": 8},
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{"name": "PMC8_EVENT_SEL", "msb": 23, "lsb": 16},
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{"name": "PMC9_EVENT_SEL", "msb": 31, "lsb": 24}
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]}]},
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{"index": 0, "name": "PMCR1_GL1", "fullname": "Performance Monitor Control Register 1 (GL1)", "enc": [3, 1, 15, 8, 2 ], "width": 64},
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{"index": 0, "name": "PMSR_EL1", "fullname": "Performance Monitor Status Register", "enc": [3, 1, 15, 13, 0 ], "width": 64,
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"fieldsets": [{"fields": [
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{"name": "PMC0_OVERFLOW", "msb": 0, "lsb": 0},
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{"name": "PMC1_OVERFLOW", "msb": 1, "lsb": 1},
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{"name": "PMC2_OVERFLOW", "msb": 2, "lsb": 2},
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{"name": "PMC3_OVERFLOW", "msb": 3, "lsb": 3},
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{"name": "PMC4_OVERFLOW", "msb": 4, "lsb": 4},
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{"name": "PMC5_OVERFLOW", "msb": 5, "lsb": 5},
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{"name": "PMC6_OVERFLOW", "msb": 6, "lsb": 6},
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{"name": "PMC7_OVERFLOW", "msb": 7, "lsb": 7},
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{"name": "PMC8_OVERFLOW", "msb": 8, "lsb": 8},
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{"name": "PMC9_OVERFLOW", "msb": 9, "lsb": 9}
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]}]},
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{"index": 0, "name": "PMC0_EL1", "fullname": "Performance Monitor Counter 0", "enc": [3, 2, 15, 0, 0 ], "width": 64},
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{"index": 0, "name": "PMC1_EL1", "fullname": "Performance Monitor Counter 1", "enc": [3, 2, 15, 1, 0 ], "width": 64},
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{"index": 0, "name": "PMC2_EL1", "fullname": "Performance Monitor Counter 2", "enc": [3, 2, 15, 2, 0 ], "width": 64},
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{"index": 0, "name": "PMC3_EL1", "fullname": "Performance Monitor Counter 3", "enc": [3, 2, 15, 3, 0 ], "width": 64},
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{"index": 0, "name": "PMC4_EL1", "fullname": "Performance Monitor Counter 4", "enc": [3, 2, 15, 4, 0 ], "width": 64},
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{"index": 0, "name": "PMC5_EL1", "fullname": "Performance Monitor Counter 5", "enc": [3, 2, 15, 5, 0 ], "width": 64},
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{"index": 0, "name": "PMC6_EL1", "fullname": "Performance Monitor Counter 6", "enc": [3, 2, 15, 6, 0 ], "width": 64},
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{"index": 0, "name": "PMC7_EL1", "fullname": "Performance Monitor Counter 7", "enc": [3, 2, 15, 7, 0 ], "width": 64},
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{"index": 0, "name": "PMC8_EL1", "fullname": "Performance Monitor Counter 8", "enc": [3, 2, 15, 9, 0 ], "width": 64},
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{"index": 0, "name": "PMC9_EL1", "fullname": "Performance Monitor Counter 9", "enc": [3, 2, 15, 10, 0 ], "width": 64},
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{"index": 0, "name": "LSU_ERR_STS_EL1", "fullname": "Load-Store Unit Error Status", "enc": [3, 3, 15, 0, 0 ], "width": 64},
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{"index": 0, "name": "E_LSU_ERR_STS_EL1", "fullname": "Load-Store Unit Error Status (E-core)", "enc": [3, 3, 15, 2, 0 ], "width": 64},
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{"index": 0, "name": "LSU_ERR_CTL_EL1", "fullname": "Load-Store Unit Error Control", "enc": [3, 3, 15, 1, 0 ], "width": 64},
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{"index": 0, "name": "L2C_ERR_STS_EL1", "fullname": "L2 Cache Error Status", "enc": [3, 3, 15, 8, 0 ], "width": 64},
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{"index": 0, "name": "L2C_ERR_ADR_EL1", "fullname": "L2 Cache Address", "enc": [3, 3, 15, 9, 0 ], "width": 64},
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{"index": 0, "name": "L2C_ERR_INF_EL1", "fullname": "L2 Cache Error Information", "enc": [3, 3, 15, 10, 0 ], "width": 64},
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{"index": 0, "name": "FED_ERR_STS_EL1", "fullname": "FED Error Status", "enc": [3, 4, 15, 0, 0 ], "width": 64},
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{"index": 0, "name": "E_FED_ERR_STS_EL1", "fullname": "FED Error Status (E-Core)", "enc": [3, 4, 15, 0, 2 ], "width": 64},
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{"index": 0, "name": "APCTL_EL1", "fullname": "Pointer Authentication Control", "enc": [3, 4, 15, 0, 4 ], "width": 64},
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{"index": 0, "name": "SPR_LOCKDOWN_EL1", "fullname": "SPR Lockdown", "enc": [3, 4, 15, 0, 5 ], "width": 64},
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{"index": 0, "name": "KERNKEYLO_EL1", "fullname": "Pointer Authentication Kernel Key Low", "enc": [3, 4, 15, 1, 0 ], "width": 64},
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{"index": 0, "name": "KERNKEYHI_EL1", "fullname": "Pointer Authentication Kernel Key High", "enc": [3, 4, 15, 1, 1 ], "width": 64},
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{"index": 0, "name": "VMSA_LOCK_EL1", "fullname": "Virtual Memory System Architecture Lock", "enc": [3, 4, 15, 1, 2 ], "width": 64},
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{"index": 0, "name": "AMX_STATE_EL12", "fullname": "AMX State (EL1)", "enc": [3, 4, 15, 1, 3 ], "width": 64},
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{"index": 0, "name": "AMX_CONFIG_EL1", "fullname": "AMX Config (EL1)", "enc": [3, 4, 15, 1, 4 ], "width": 64,
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"fieldsets": [{"fields": [
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{"name": "EN", "msb": 63, "lsb": 63}
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]}]},
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{"index": 0, "name": "APRR_EL0", "fullname": "APRR EL0", "enc": [3, 4, 15, 2, 0 ], "width": 64},
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{"index": 0, "name": "APRR_EL1", "fullname": "APRR EL1", "enc": [3, 4, 15, 2, 1 ], "width": 64},
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{"index": 0, "name": "CTRR_LOCK_EL1", "fullname": "CTRR Lock", "enc": [3, 4, 15, 2, 2 ], "width": 64},
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{"index": 0, "name": "CTRR_A_LWR_EL1", "fullname": "CTRR A Lower Address (EL1)", "enc": [3, 4, 15, 2, 3 ], "width": 64},
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{"index": 0, "name": "CTRR_A_UPR_EL1", "fullname": "CTRR A Upper Address (EL1)", "enc": [3, 4, 15, 2, 4 ], "width": 64},
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{"index": 0, "name": "CTRR_CTL_EL1", "fullname": "CTRR Control (EL1)", "enc": [3, 4, 15, 2, 5 ], "width": 64},
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{"index": 0, "name": "VMSA_LOCK_EL12", "fullname": "Virtual Memory System Architecture Lock (EL12)", "enc": [3, 4, 15, 2, 6 ], "width": 64},
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{"index": 0, "name": "APRR_JIT_MASK_EL2", "fullname": "APRR JIT Mask", "enc": [3, 4, 15, 2, 7 ], "width": 64},
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{"index": 0, "name": "AMX_CONFIG_EL12", "fullname": "AMX Config (EL12)", "enc": [3, 4, 15, 4, 6 ], "width": 64},
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{"index": 0, "name": "AMX_CTL_EL2", "fullname": "AMX Control (EL2)", "enc": [3, 4, 15, 4, 7 ], "width": 64,
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"fieldsets": [{"fields": [
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{"name": "EN", "msb": 63, "lsb": 63},
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{"name": "EN_EL1", "msb": 62, "lsb": 62}
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]}]},
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{"index": 0, "name": "CORE_INDEX", "fullname": "Core index in cluster", "enc": [3, 4, 15, 5, 0 ], "width": 64},
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{"index": 0, "name": "SPRR_PPERM_EL20_SILLY_THING", "fullname": "SPRR Permission Configuration Register (EL20, useless)", "enc": [3, 4, 15, 5, 1 ], "width": 64},
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{"index": 0, "name": "SPRR_UPERM_EL02", "fullname": "SPRR User Permission Configuration Register (EL02)", "enc": [3, 4, 15, 5, 2 ], "width": 64},
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{"index": 0, "name": "SPRR_UMPRR_EL2", "fullname": "SPRR User MPRR (EL2)", "enc": [3, 4, 15, 7, 0 ], "width": 32},
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{"index": 0, "name": "SPRR_UPERM_SH1_EL2", "fullname": "SPRR User Permission SH1 (EL2)", "enc": [3, 4, 15, 7, 1 ], "width": 32},
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{"index": 0, "name": "SPRR_UPERM_SH2_EL2", "fullname": "SPRR User Permission SH2 (EL2)", "enc": [3, 4, 15, 7, 2 ], "width": 32},
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{"index": 0, "name": "SPRR_UPERM_SH3_EL2", "fullname": "SPRR User Permission SH3 (EL2)", "enc": [3, 4, 15, 7, 3 ], "width": 32},
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{"index": 0, "name": "SPRR_UMPRR_EL12", "fullname": "SPRR User MPRR (EL12)", "enc": [3, 4, 15, 8, 0 ], "width": 32},
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{"index": 0, "name": "SPRR_UPERM_SH1_EL12", "fullname": "SPRR User Permission SH1 (EL12)", "enc": [3, 4, 15, 8, 1 ], "width": 32},
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{"index": 0, "name": "SPRR_UPERM_SH2_EL12", "fullname": "SPRR User Permission SH2 (EL12)", "enc": [3, 4, 15, 8, 2 ], "width": 32},
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{"index": 0, "name": "SPRR_UPERM_SH3_EL12", "fullname": "SPRR User Permission SH3 (EL12)", "enc": [3, 4, 15, 8, 3 ], "width": 32},
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{"index": 0, "name": "CTRR_A_LWR_EL12", "fullname": "CTRR A Lower Address (EL12)", "enc": [3, 4, 15, 9, 0 ], "width": 64},
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{"index": 0, "name": "CTRR_A_UPR_EL12", "fullname": "CTRR A Upper Address (EL12)", "enc": [3, 4, 15, 9, 1 ], "width": 64},
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{"index": 0, "name": "CTRR_B_LWR_EL12", "fullname": "CTRR B Lower Address (EL12)", "enc": [3, 4, 15, 9, 2 ], "width": 64},
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{"index": 0, "name": "CTRR_B_UPR_EL12", "fullname": "CTRR B Upper Address (EL12)", "enc": [3, 4, 15, 9, 3 ], "width": 64},
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{"index": 0, "name": "CTRR_CTL_EL12", "fullname": "CTRR Control (EL12)", "enc": [3, 4, 15, 9, 4 ], "width": 64},
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{"index": 0, "name": "CTRR_LOCK_EL12", "fullname": "CTRR Lock (EL12)", "enc": [3, 4, 15, 9, 5 ], "width": 64},
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{"index": 0, "name": "SIQ_CFG_EL1", "fullname": "System Interrupt Configuration (EL1)", "enc": [3, 4, 15, 10, 4 ], "width": 64},
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{"index": 0, "name": "ACNTPCT_EL0", "fullname": "Physical timer counter register (pre-spec CNTPCTSS_EL0)", "enc": [3, 4, 15, 10, 5 ], "width": 64},
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{"index": 0, "name": "ACNTVCT_EL0", "fullname": "Virtual timer counter register (pre-spec CNTVCTSS_EL0)", "enc": [3, 4, 15, 10, 6 ], "width": 64},
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{"index": 0, "name": "CTRR_A_LWR_EL2", "fullname": "CTRR A Lower Address (EL2)", "enc": [3, 4, 15, 11, 0 ], "width": 64},
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{"index": 0, "name": "CTRR_A_UPR_EL2", "fullname": "CTRR A Upper Address (EL2)", "enc": [3, 4, 15, 11, 1 ], "width": 64},
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{"index": 0, "name": "CTRR_CTL_EL2", "fullname": "CTRR Control (EL2)", "enc": [3, 4, 15, 11, 4 ], "width": 64},
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{"index": 0, "name": "CTRR_LOCK_EL2", "fullname": "CTRR Lock", "enc": [3, 4, 15, 11, 5 ], "width": 64},
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{"index": 0, "name": "JCTL_EL0", "fullname": "JITBox Control (EL0)", "enc": [3, 4, 15, 15, 6 ], "width": 64},
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{"index": 0, "name": "IPI_RR_LOCAL_EL1", "fullname": "IPI Request Register (Local)", "enc": [3, 5, 15, 0, 0 ], "width": 64},
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{"index": 0, "name": "IPI_RR_GLOBAL_EL1", "fullname": "IPI Request Register (Global)", "enc": [3, 5, 15, 0, 1 ], "width": 64},
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{"index": 0, "name": "DPC_ERR_STS_EL1", "fullname": "DPC Error Status", "enc": [3, 5, 15, 0, 5 ], "width": 64},
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{"index": 0, "name": "IPI_SR_EL1", "fullname": "IPI Status Register", "enc": [3, 5, 15, 1, 1 ], "width": 64,
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"fieldsets": [{"fields": [
|
|
{"name": "PENDING", "msb": 0, "lsb": 0}
|
|
]}]},
|
|
{"index": 0, "name": "VM_TMR_LR_EL2", "fullname": "VM Timer Link Register", "enc": [3, 5, 15, 1, 2 ], "width": 64},
|
|
{"index": 0, "name": "VM_TMR_FIQ_ENA_EL2", "fullname": "VM Timer FIQ Enable", "enc": [3, 5, 15, 1, 3 ], "width": 64,
|
|
"fieldsets": [{"fields": [
|
|
{"name": "ENA_V", "msb": 0, "lsb": 0},
|
|
{"name": "ENA_P", "msb": 1, "lsb": 1}
|
|
]}]},
|
|
{"index": 0, "name": "AWL_SCRATCH_EL1", "fullname": "AWL Scratch Register", "enc": [3, 5, 15, 2, 6 ], "width": 64},
|
|
{"index": 0, "name": "IPI_CR_EL1", "fullname": "IPI Control Register", "enc": [3, 5, 15, 3, 1 ], "width": 64},
|
|
{"index": 0, "name": "ACC_CFG_EL1", "fullname": "Apple Core Cluster Configuration", "enc": [3, 5, 15, 4, 0 ], "width": 64},
|
|
{"index": 0, "name": "CYC_OVRD_EL1", "fullname": "Cyclone Override", "enc": [3, 5, 15, 5, 0 ], "width": 64},
|
|
{"index": 0, "name": "ACC_OVRD_EL1", "fullname": "Apple Core Cluster Override", "enc": [3, 5, 15, 6, 0 ], "width": 64},
|
|
{"index": 0, "name": "ACC_EBLK_OVRD_EL1", "fullname": "Apple Core Cluster E-Block Override", "enc": [3, 5, 15, 6, 1 ], "width": 64},
|
|
{"index": 0, "name": "MMU_ERR_STS_EL1", "fullname": "MMU Error Status", "enc": [3, 6, 15, 0, 0 ], "width": 64},
|
|
{"index": 0, "name": "AFSR1_GL1", "fullname": "Auxiliary Fault Status Register 1 (GL1)", "enc": [3, 6, 15, 0, 1 ], "width": 64},
|
|
{"index": 0, "name": "AFSR1_GL2", "fullname": "Auxiliary Fault Status Register 1 (GL2)", "enc": [3, 6, 15, 0, 2 ], "width": 64},
|
|
{"index": 0, "name": "AFSR1_GL12", "fullname": "Auxiliary Fault Status Register 1 (GL12)", "enc": [3, 6, 15, 0, 3 ], "width": 64},
|
|
{"index": 0, "name": "SPRR_CONFIG_EL1", "fullname": "SPRR Configuration Register (EL1)", "enc": [3, 6, 15, 1, 0 ], "width": 64,
|
|
"fieldsets": [{"fields": [
|
|
{"name": "EN", "msb": 0, "lsb": 0},
|
|
{"name": "LOCK_CONFIG", "msb": 1, "lsb": 1},
|
|
{"name": "LOCK_PERM", "msb": 4, "lsb": 4},
|
|
{"name": "LOCK_KERNEL_PERM", "msb": 5, "lsb": 5}
|
|
]}]},
|
|
{"index": 0, "name": "GXF_CONFIG_EL1", "fullname": "GXF Configuration Register (EL1)", "enc": [3, 6, 15, 1, 2 ], "width": 64,
|
|
"fieldsets": [{"fields": [
|
|
{"name": "EN", "msb": 0, "lsb": 0}
|
|
]}]},
|
|
{"index": 0, "name": "SPRR_AMRANGE_EL1", "fullname": "SPRR AM Range (EL1)", "enc": [3, 6, 15, 1, 3 ], "width": 64},
|
|
{"index": 0, "name": "GXF_CONFIG_EL2", "fullname": "GXF Configuration Register (EL2)", "enc": [3, 6, 15, 1, 4 ], "width": 64},
|
|
{"index": 0, "name": "SPRR_UPERM_EL0", "fullname": "SPRR User Permission Configuration Register (EL0)", "enc": [3, 6, 15, 1, 5 ], "width": 64},
|
|
{"index": 0, "name": "SPRR_PPERM_EL1", "fullname": "SPRR Kernel Permission Configuration Register (EL1)", "enc": [3, 6, 15, 1, 6 ], "width": 64},
|
|
{"index": 0, "name": "SPRR_PPERM_EL2", "fullname": "SPRR Kernel Permission Configuration Register (EL2)", "enc": [3, 6, 15, 1, 7 ], "width": 64},
|
|
{"index": 0, "name": "E_MMU_ERR_STS_EL1", "fullname": "MMU Error Status (E-Core)", "enc": [3, 6, 15, 2, 0 ], "width": 64},
|
|
{"index": 0, "name": "APGAKeyLo_EL12", "fullname": "Pointer Authentication Key A for Code Low (EL12)", "enc": [3, 6, 15, 2, 1 ], "width": 64},
|
|
{"index": 0, "name": "APGAKeyHi_EL12", "fullname": "Pointer Authentication Key A for Code High (EL12)", "enc": [3, 6, 15, 2, 2 ], "width": 64},
|
|
{"index": 0, "name": "KERNKEYLO_EL12", "fullname": "Pointer Authentication Kernel Key Low (EL12)", "enc": [3, 6, 15, 2, 3 ], "width": 64},
|
|
{"index": 0, "name": "KERNKEYHI_EL12", "fullname": "Pointer Authentication Kernel Key High (EL12)", "enc": [3, 6, 15, 2, 4 ], "width": 64},
|
|
{"index": 0, "name": "AFPCR_EL0", "fullname": "Apple Floating-Point Control Register", "enc": [3, 6, 15, 2, 5 ], "width": 64},
|
|
{"index": 0, "name": "AIDR2_EL1", "fullname": "Apple ID Register 2", "enc": [3, 6, 15, 2, 7 ], "width": 64},
|
|
{"index": 0, "name": "SPRR_UMPRR_EL1", "fullname": "SPRR User MPRR (EL1)", "enc": [3, 6, 15, 3, 0 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_PMPRR_EL1", "fullname": "SPRR Kernel MPRR (EL1)", "enc": [3, 6, 15, 3, 1 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_PMPRR_EL2", "fullname": "SPRR Kernel MPRR (EL2)", "enc": [3, 6, 15, 3, 2 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_UPERM_SH1_EL1", "fullname": "SPRR User Permission SH1 (EL1)", "enc": [3, 6, 15, 3, 3 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_UPERM_SH2_EL1", "fullname": "SPRR User Permission SH2 (EL1)", "enc": [3, 6, 15, 3, 4 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_UPERM_SH3_EL1", "fullname": "SPRR User Permission SH3 (EL1)", "enc": [3, 6, 15, 3, 5 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_PPERM_SH1_EL1", "fullname": "SPRR Kernel Permission SH1 (EL1)", "enc": [3, 6, 15, 4, 2 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_PPERM_SH2_EL1", "fullname": "SPRR Kernel Permission SH2 (EL1)", "enc": [3, 6, 15, 4, 3 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_PPERM_SH3_EL1", "fullname": "SPRR Kernel Permission SH3 (EL1)", "enc": [3, 6, 15, 4, 4 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_PPERM_SH1_EL2", "fullname": "SPRR Kernel Permission SH1 (EL2)", "enc": [3, 6, 15, 5, 1 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_PPERM_SH2_EL2", "fullname": "SPRR Kernel Permission SH2 (EL2)", "enc": [3, 6, 15, 5, 2 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_PPERM_SH3_EL2", "fullname": "SPRR Kernel Permission SH3 (EL2)", "enc": [3, 6, 15, 5, 3 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_PMPRR_EL12", "fullname": "SPRR Kernel MPRR (EL12)", "enc": [3, 6, 15, 6, 0 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_PPERM_SH1_EL12", "fullname": "SPRR Kernel Permission SH1 (EL12)", "enc": [3, 6, 15, 6, 1 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_PPERM_SH2_EL12", "fullname": "SPRR Kernel Permission SH2 (EL12)", "enc": [3, 6, 15, 6, 2 ], "width": 32},
|
|
{"index": 0, "name": "SPRR_PPERM_SH3_EL12", "fullname": "SPRR Kernel Permission SH3 (EL12)", "enc": [3, 6, 15, 6, 3 ], "width": 32},
|
|
{"index": 0, "name": "APIAKeyLo_EL12", "fullname": "Pointer Authentication Key A for Instruction Low (EL12)", "enc": [3, 6, 15, 7, 0 ], "width": 64},
|
|
{"index": 0, "name": "APIAKeyHi_EL12", "fullname": "Pointer Authentication Key A for Instruction High (EL12)", "enc": [3, 6, 15, 7, 1 ], "width": 64},
|
|
{"index": 0, "name": "APIBKeyLo_EL12", "fullname": "Pointer Authentication Key A for Instruction Low (EL12)", "enc": [3, 6, 15, 7, 2 ], "width": 64},
|
|
{"index": 0, "name": "APIBKeyHi_EL12", "fullname": "Pointer Authentication Key A for Instruction High (EL12)", "enc": [3, 6, 15, 7, 3 ], "width": 64},
|
|
{"index": 0, "name": "APDAKeyLo_EL12", "fullname": "Pointer Authentication Key A for Data Low (EL12)", "enc": [3, 6, 15, 7, 4 ], "width": 64},
|
|
{"index": 0, "name": "APDAKeyHi_EL12", "fullname": "Pointer Authentication Key A for Data High (EL12)", "enc": [3, 6, 15, 7, 5 ], "width": 64},
|
|
{"index": 0, "name": "APDBKeyLo_EL12", "fullname": "Pointer Authentication Key A for Data Low (EL12)", "enc": [3, 6, 15, 7, 6 ], "width": 64},
|
|
{"index": 0, "name": "APDBKeyHi_EL12", "fullname": "Pointer Authentication Key A for Data High (EL12)", "enc": [3, 6, 15, 7, 7 ], "width": 64},
|
|
{"index": 0, "name": "GXF_STATUS_EL1", "fullname": "GXF Status Register (CurrentG)", "enc": [3, 6, 15, 8, 0 ], "width": 64,
|
|
"fieldsets": [{"fields": [
|
|
{"name": "GUARDED", "msb": 0, "lsb": 0}
|
|
]}]},
|
|
{"index": 0, "name": "GXF_ENTRY_EL1", "fullname": "GXF genter Entry Vector Register (EL1)", "enc": [3, 6, 15, 8, 1 ], "width": 64},
|
|
{"index": 0, "name": "GXF_PABENTRY_EL1", "fullname": "GXF Abort Vector Register (EL1)", "enc": [3, 6, 15, 8, 2 ], "width": 64},
|
|
{"index": 0, "name": "ASPSR_EL1", "fullname": "ASPSR (EL1)", "enc": [3, 6, 15, 8, 3 ], "width": 64},
|
|
{"index": 0, "name": "VBAR_GL12", "fullname": "Vector Base Address Register (GL12)", "enc": [3, 6, 15, 9, 2 ], "width": 64},
|
|
{"index": 0, "name": "SPSR_GL12", "fullname": "Saved Program Status Register (GL12)", "enc": [3, 6, 15, 9, 3 ], "width": 64},
|
|
{"index": 0, "name": "ASPSR_GL12", "fullname": "ASPSR (GL12)", "enc": [3, 6, 15, 9, 4 ], "width": 64},
|
|
{"index": 0, "name": "ESR_GL12", "fullname": "Exception Syndrome Register (GL12)", "enc": [3, 6, 15, 9, 5 ], "width": 64},
|
|
{"index": 0, "name": "ELR_GL12", "fullname": "Exception Link Register (GL12)", "enc": [3, 6, 15, 9, 6 ], "width": 64},
|
|
{"index": 0, "name": "FAR_GL12", "fullname": "Fault Address Register (GL12)", "enc": [3, 6, 15, 9, 7 ], "width": 64},
|
|
{"index": 0, "name": "SP_GL12", "fullname": "Stack Pointer Register (GL12)", "enc": [3, 6, 15, 10, 0 ], "width": 64},
|
|
{"index": 0, "name": "TPIDR_GL1", "fullname": "Software Thread ID Register (GL1)", "enc": [3, 6, 15, 10, 1 ], "width": 64},
|
|
{"index": 0, "name": "VBAR_GL1", "fullname": "Vector Base Address Register (GL1)", "enc": [3, 6, 15, 10, 2 ], "width": 64},
|
|
{"index": 0, "name": "SPSR_GL1", "fullname": "Saved Program Status Register (GL1)", "enc": [3, 6, 15, 10, 3 ], "width": 64},
|
|
{"index": 0, "name": "ASPSR_GL1", "fullname": "ASPSR (GL1)", "enc": [3, 6, 15, 10, 4 ], "width": 64},
|
|
{"index": 0, "name": "ESR_GL1", "fullname": "Exception Syndrome Register (GL1)", "enc": [3, 6, 15, 10, 5 ], "width": 64},
|
|
{"index": 0, "name": "ELR_GL1", "fullname": "Exception Link Register (GL1)", "enc": [3, 6, 15, 10, 6 ], "width": 64},
|
|
{"index": 0, "name": "FAR_GL1", "fullname": "Fault Address Register (GL1)", "enc": [3, 6, 15, 10, 7 ], "width": 64},
|
|
{"index": 0, "name": "TPIDR_GL2", "fullname": "Software Thread ID Register (GL2)", "enc": [3, 6, 15, 11, 1 ], "width": 64},
|
|
{"index": 0, "name": "VBAR_GL2", "fullname": "Vector Base Address Register (GL2)", "enc": [3, 6, 15, 11, 2 ], "width": 64},
|
|
{"index": 0, "name": "SPSR_GL2", "fullname": "Saved Program Status Register (GL2)", "enc": [3, 6, 15, 11, 3 ], "width": 64},
|
|
{"index": 0, "name": "ASPSR_GL2", "fullname": "ASPSR (GL2)", "enc": [3, 6, 15, 11, 4 ], "width": 64},
|
|
{"index": 0, "name": "ESR_GL2", "fullname": "Exception Syndrome Register (GL2)", "enc": [3, 6, 15, 11, 5 ], "width": 64},
|
|
{"index": 0, "name": "ELR_GL2", "fullname": "Exception Link Register (GL2)", "enc": [3, 6, 15, 11, 6 ], "width": 64},
|
|
{"index": 0, "name": "FAR_GL2", "fullname": "Fault Address Register (GL2)", "enc": [3, 6, 15, 11, 7 ], "width": 64},
|
|
{"index": 0, "name": "GXF_ENTRY_EL2", "fullname": "GXF genter Entry Vector Register (EL2)", "enc": [3, 6, 15, 12, 0 ], "width": 64},
|
|
{"index": 0, "name": "GXF_PABENTRY_EL2", "fullname": "GXF Abort Vector Register (EL2)", "enc": [3, 6, 15, 12, 1 ], "width": 64},
|
|
{"index": 0, "name": "APCTL_EL2", "fullname": "Pointer Authentication Control (EL2)", "enc": [3, 6, 15, 12, 2 ], "width": 64},
|
|
{"index": 0, "name": "APSTS_EL2_MAYBE", "fullname": "Pointer Authentication Status (EL2, maybe)", "enc": [3, 6, 15, 12, 3 ], "width": 64},
|
|
{"index": 0, "name": "APSTS_EL1", "fullname": "Pointer Authentication Status", "enc": [3, 6, 15, 12, 4 ], "width": 64},
|
|
{"index": 0, "name": "SPRR_CONFIG_EL2", "fullname": "SPRR Configuration Register (EL2)", "enc": [3, 6, 15, 14, 2 ], "width": 64},
|
|
{"index": 0, "name": "SPRR_AMRANGE_EL2", "fullname": "SPRR AM Range (EL2)", "enc": [3, 6, 15, 14, 3 ], "width": 64},
|
|
{"index": 0, "name": "VMKEYLO_EL2", "fullname": "Pointer Authentication VM Machine Key Low", "enc": [3, 6, 15, 14, 4 ], "width": 64},
|
|
{"index": 0, "name": "VMKEYHI_EL2", "fullname": "Pointer Authentication VM Machine Key High", "enc": [3, 6, 15, 14, 5 ], "width": 64},
|
|
{"index": 0, "name": "ACTLR_EL12", "fullname": "Auxiliary Control Register (EL12)", "enc": [3, 6, 15, 14, 6 ], "width": 64},
|
|
{"index": 0, "name": "APSTS_EL12", "fullname": "Pointer Authentication Status (EL12)", "enc": [3, 6, 15, 14, 7 ], "width": 64},
|
|
{"index": 0, "name": "APCTL_EL12", "fullname": "Pointer Authentication Control (EL12)", "enc": [3, 6, 15, 15, 0 ], "width": 64},
|
|
{"index": 0, "name": "GXF_CONFIG_EL12", "fullname": "GXF Configuration Register (EL12)", "enc": [3, 6, 15, 15, 1 ], "width": 64},
|
|
{"index": 0, "name": "GXF_ENTRY_EL12", "fullname": "GXF genter Entry Vector Register (EL12)", "enc": [3, 6, 15, 15, 2 ], "width": 64},
|
|
{"index": 0, "name": "GXF_PABENTRY_EL12", "fullname": "GXF Abort Vector Register (EL12)", "enc": [3, 6, 15, 15, 3 ], "width": 64},
|
|
{"index": 0, "name": "SPRR_CONFIG_EL12", "fullname": "SPRR Configuration Register (EL12)", "enc": [3, 6, 15, 15, 4 ], "width": 64},
|
|
{"index": 0, "name": "SPRR_AMRANGE_EL12", "fullname": "SPRR AM Range (EL12)", "enc": [3, 6, 15, 15, 5 ], "width": 64},
|
|
{"index": 0, "name": "SPRR_PPERM_EL12", "fullname": "SPRR Permission Configuration Register (EL12)", "enc": [3, 6, 15, 15, 7 ], "width": 64},
|
|
{"index": 0, "name": "UPMCR0_EL1", "fullname": "Uncore Performance Monitor Control Register 0", "enc": [3, 7, 15, 0, 4 ], "width": 64},
|
|
{"index": 0, "name": "UPMESR0_EL1", "fullname": "Uncore Performance Monitor Event Selection Register 0", "enc": [3, 7, 15, 1, 4 ], "width": 64},
|
|
{"index": 0, "name": "UPMECM0_EL1", "fullname": "Uncore Performance Monitor Event Core Mask 0", "enc": [3, 7, 15, 3, 4 ], "width": 64},
|
|
{"index": 0, "name": "UPMECM1_EL1", "fullname": "Uncore Performance Monitor Event Core Mask 1", "enc": [3, 7, 15, 4, 4 ], "width": 64},
|
|
{"index": 0, "name": "UPMPCM_EL1", "fullname": "Uncore Performance Monitor PMI Core Mask", "enc": [3, 7, 15, 5, 4 ], "width": 64},
|
|
{"index": 0, "name": "UPMSR_EL1", "fullname": "Uncore Performance Monitor Status Register", "enc": [3, 7, 15, 6, 4 ], "width": 64},
|
|
{"index": 0, "name": "UPMECM2_EL1", "fullname": "Uncore Performance Monitor Event Core Mask 2", "enc": [3, 7, 15, 8, 5 ], "width": 64},
|
|
{"index": 0, "name": "UPMECM3_EL1", "fullname": "Uncore Performance Monitor Event Core Mask 3", "enc": [3, 7, 15, 9, 5 ], "width": 64},
|
|
{"index": 0, "name": "UPMESR1_EL1", "fullname": "Uncore Performance Monitor Event Selection Register 1", "enc": [3, 7, 15, 11, 5 ], "width": 64},
|
|
{"index": 0, "name": "UPMC0_EL1", "fullname": "Uncore Performance Monitor Counter 0", "enc": [3, 7, 15, 7, 4 ], "width": 64},
|
|
{"index": 0, "name": "UPMC1_EL1", "fullname": "Uncore Performance Monitor Counter 1", "enc": [3, 7, 15, 8, 4 ], "width": 64},
|
|
{"index": 0, "name": "UPMC2_EL1", "fullname": "Uncore Performance Monitor Counter 2", "enc": [3, 7, 15, 9, 4 ], "width": 64},
|
|
{"index": 0, "name": "UPMC3_EL1", "fullname": "Uncore Performance Monitor Counter 3", "enc": [3, 7, 15, 10, 4 ], "width": 64},
|
|
{"index": 0, "name": "UPMC4_EL1", "fullname": "Uncore Performance Monitor Counter 4", "enc": [3, 7, 15, 11, 4 ], "width": 64},
|
|
{"index": 0, "name": "UPMC5_EL1", "fullname": "Uncore Performance Monitor Counter 5", "enc": [3, 7, 15, 12, 4 ], "width": 64},
|
|
{"index": 0, "name": "UPMC6_EL1", "fullname": "Uncore Performance Monitor Counter 6", "enc": [3, 7, 15, 13, 4 ], "width": 64},
|
|
{"index": 0, "name": "UPMC7_EL1", "fullname": "Uncore Performance Monitor Counter 7", "enc": [3, 7, 15, 14, 4 ], "width": 64},
|
|
{"index": 0, "name": "UPMC8_EL1", "fullname": "Uncore Performance Monitor Counter 8", "enc": [3, 7, 15, 0, 5 ], "width": 64},
|
|
{"index": 0, "name": "UPMC9_EL1", "fullname": "Uncore Performance Monitor Counter 9", "enc": [3, 7, 15, 1, 5 ], "width": 64},
|
|
{"index": 0, "name": "UPMC10_EL1", "fullname": "Uncore Performance Monitor Counter 10", "enc": [3, 7, 15, 2, 5 ], "width": 64},
|
|
{"index": 0, "name": "UPMC11_EL1", "fullname": "Uncore Performance Monitor Counter 11", "enc": [3, 7, 15, 3, 5 ], "width": 64},
|
|
{"index": 0, "name": "UPMC12_EL1", "fullname": "Uncore Performance Monitor Counter 12", "enc": [3, 7, 15, 4, 5 ], "width": 64},
|
|
{"index": 0, "name": "UPMC13_EL1", "fullname": "Uncore Performance Monitor Counter 13", "enc": [3, 7, 15, 5, 5 ], "width": 64},
|
|
{"index": 0, "name": "UPMC14_EL1", "fullname": "Uncore Performance Monitor Counter 14", "enc": [3, 7, 15, 6, 5 ], "width": 64},
|
|
{"index": 0, "name": "UPMC15_EL1", "fullname": "Uncore Performance Monitor Counter 15", "enc": [3, 7, 15, 7, 5 ], "width": 64},
|
|
{"index": 0, "name": "HACR_EL2", "fullname": "Hypervisor Auxiliary Control Register", "enc": [3, 4, 1, 1, 7 ], "width": 64,
|
|
"fieldsets": [{"fields": [
|
|
{"name": "TRAP_CPU_EXT", "msb": 0, "lsb": 0},
|
|
{"name": "TRAP_AIDR", "msb": 4, "lsb": 4},
|
|
{"name": "TRAP_AMX", "msb": 10, "lsb": 10},
|
|
{"name": "TRAP_SPRR", "msb": 11, "lsb": 11},
|
|
{"name": "TRAP_GXF", "msb": 13, "lsb": 13},
|
|
{"name": "TRAP_CTRR", "msb": 14, "lsb": 14},
|
|
{"name": "TRAP_IPI", "msb": 16, "lsb": 16},
|
|
{"name": "TRAP_s3_4_c15_c5z6_x", "msb": 18, "lsb": 18},
|
|
{"name": "TRAP_s3_4_c15_c0z12_5", "msb": 19, "lsb": 19},
|
|
{"name": "GIC_CNTV", "msb": 20, "lsb": 20},
|
|
{"name": "TRAP_s3_4_c15_c10_4", "msb": 25, "lsb": 25},
|
|
{"name": "TRAP_SERROR_INFO", "msb": 48, "lsb": 48},
|
|
{"name": "TRAP_EHID", "msb": 49, "lsb": 49},
|
|
{"name": "TRAP_HID", "msb": 50, "lsb": 50},
|
|
{"name": "TRAP_s3_0_c15_c12_1z2", "msb": 51, "lsb": 51},
|
|
{"name": "TRAP_ACC", "msb": 52, "lsb": 52},
|
|
{"name": "TRAP_PMUV3", "msb": 56, "lsb": 56},
|
|
{"name": "TRAP_PM", "msb": 57, "lsb": 57},
|
|
{"name": "TRAP_UPM", "msb": 58, "lsb": 58},
|
|
{"name": "TRAP_s3_1z7_c15_cx_3", "msb": 59, "lsb": 59}
|
|
]}]}
|
|
]
|