mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-24 07:33:02 +00:00
9f846b1e41
Right now, we assume the boot cpu is cpu0. That is not true on m3 max, where it is CPU 4. To figure out which CPU is the boot CPU, we check to see which CPU is running before we start any other CPUs, and record the MPIDR/idx. Without this patch, four issues happen on m3 max: 1. We try to start the boot CPU again, crashing it 2. We skip the real CPU 0 3. We start m1n1 again on CPU0 when we boot it 4. We enable interrupts on CPU0 because we think it's the primary CPU. Signed-off-by: Daniel Berlin <dberlin@dberlin.org>
43 lines
989 B
C
43 lines
989 B
C
/* SPDX-License-Identifier: MIT */
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#ifndef __SMP_H__
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#define __SMP_H__
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#include "types.h"
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#include "utils.h"
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#define MAX_CPUS 24
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#define SECONDARY_STACK_SIZE 0x10000
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extern u8 *secondary_stacks[MAX_CPUS];
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void smp_secondary_entry(void);
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void smp_start_secondaries(void);
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void smp_stop_secondaries(bool deep_sleep);
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#define smp_call0(i, f) smp_call4(i, f, 0, 0, 0, 0)
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#define smp_call1(i, f, a) smp_call4(i, f, a, 0, 0, 0)
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#define smp_call2(i, f, a, b) smp_call4(i, f, a, b, 0, 0)
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#define smp_call3(i, f, a, b, c) smp_call4(i, f, a, b, c, 0)
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void smp_call4(int cpu, void *func, u64 arg0, u64 arg1, u64 arg2, u64 arg3);
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u64 smp_wait(int cpu);
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bool smp_is_alive(int cpu);
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uint64_t smp_get_mpidr(int cpu);
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u64 smp_get_release_addr(int cpu);
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void smp_set_wfe_mode(bool new_mode);
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void smp_send_ipi(int cpu);
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static inline int smp_id(void)
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{
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if (in_el2())
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return mrs(TPIDR_EL2);
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else
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return mrs(TPIDR_EL1);
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}
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extern int boot_cpu_idx;
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#endif
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