mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-15 03:37:06 +00:00
116 lines
3.2 KiB
Python
Executable file
116 lines
3.2 KiB
Python
Executable file
#!/usr/bin/env python3
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# SPDX-License-Identifier: MIT
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import sys, pathlib
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sys.path.append(str(pathlib.Path(__file__).resolve().parents[1]))
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import struct
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from m1n1.setup import *
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from m1n1 import asm
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class R_ERROR(Register32):
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FLAG = 31
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STREAM = 27, 24
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CODE = 23, 0
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READ_FAULT = 4
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WRITE_FAULT = 3
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NO_PTE = 2
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NO_PMD = 1
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NO_TTBR = 0
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class R_STREAM_COMMAND(Register32):
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INVALIDATE = 20
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BUSY = 2
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class R_TCR(Register32):
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BYPASS_DAPF = 12
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BYPASS_DART = 8
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TRANSLATE_ENABLE = 7
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class R_TTBR(Register32):
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VALID = 31
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ADDR = 30, 0
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class R_REMAP(Register32):
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MAP3 = 31, 24
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MAP2 = 23, 16
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MAP1 = 15, 8
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MAP0 = 7, 0
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class DART(RegMap):
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STREAM_COMMAND = 0x20, R_STREAM_COMMAND
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STREAM_SELECT = 0x34, Register32
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ERROR = 0x40, R_ERROR
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ERROR_ADDR_LO = 0x50, Register32
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ERROR_ADDR_HI = 0x54, Register32
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REMAP = irange(0x80, 4, 4), R_REMAP
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TCR = irange(0x100, 16, 4), R_TCR
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TTBR = (irange(0x200, 16, 16), range(0, 16, 4)), R_TTBR
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def __init__(self, base):
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super().__init__(u, base)
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self.base = base
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def dump_table2(self, base, l1_addr):
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tbl = iface.readmem(l1_addr, 0x4000)
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for i in range(0, len(tbl)//8):
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pte = struct.unpack("<Q",tbl[i*8:i*8+8])[0]
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if not (pte & 0b01):
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#print(" page (%d): %08x ... %08x -> DISABLED" % (i, base + i*0x4000, base + (i+1)*0x4000))
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continue
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print(" page (%d): %08x ... %08x -> %016x [%s]" % (i, base + i*0x4000, base + (i+1)*0x4000, pte&~0b11, bin(pte&0b11)))
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def dump_table(self, base, l1_addr):
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tbl = iface.readmem(l1_addr, 0x4000)
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for i in range(0, len(tbl)//8):
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pte = struct.unpack("<Q",tbl[i*8:i*8+8])[0]
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if not (pte & 0b01):
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#print(" table (%d): %08x ... %08x -> DISABLED" % (i, base + i*0x2000000, base + (i+1)*0x2000000))
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continue
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print(" table (%d): %08x ... %08x -> %016x [%s]" % (i, base + i*0x2000000, base + (i+1)*0x2000000, pte&~0b11, bin(pte&0b11)))
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self.dump_table2(base + i*0x2000000, pte & ~0b11)
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def dump_ttbr(self, idx, ttbr):
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if not ttbr.VALID:
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return
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l1_addr = (ttbr.ADDR) << 12
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print(" TTBR%d: %09x" % (idx, l1_addr))
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self.dump_table(0, l1_addr)
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def dump_device(self, idx):
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tcr = self.TCR[idx].reg
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ttbrs = self.TTBR[idx, :]
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print(f"dev {idx:02x}: TCR={tcr!s} TTBRs = [{', '.join(map(str, ttbrs))}]")
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if tcr.TRANSLATE_ENABLE and tcr.BYPASS_DART:
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print(" mode: INVALID")
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elif tcr.TRANSLATE_ENABLE:
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print(" mode: TRANSLATE")
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for idx, ttbr in enumerate(ttbrs):
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self.dump_ttbr(idx, ttbr.reg)
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elif tcr.BYPASS_DART:
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print(" mode: BYPASS")
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else:
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print(" mode: UNKNOWN")
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def dump_all(self):
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for i in range(16):
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self.dump_device(i)
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if len(sys.argv) > 1:
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dart_addr = int(sys.argv[1], 16)
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else:
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dart_addr = 0x231304000
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# disp0 DART
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# note that there's another range just before this one
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disp0 = DART(dart_addr)
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disp0.dump_all()
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disp0.dump_regs()
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