mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-10 09:44:13 +00:00
288 lines
8.5 KiB
C
288 lines
8.5 KiB
C
/* SPDX-License-Identifier: MIT */
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#include "cpufreq.h"
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#include "adt.h"
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#include "firmware.h"
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#include "pmgr.h"
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#include "soc.h"
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#include "utils.h"
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#define CLUSTER_PSTATE 0x20020
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#define CLUSTER_PSTATE_FIXED_FREQ_PLL_RECLOCK BIT(42)
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#define CLUSTER_PSTATE_BUSY BIT(31)
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#define CLUSTER_PSTATE_SET BIT(25)
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#define CLUSTER_PSTATE_M2_APSC_DIS BIT(23)
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#define CLUSTER_PSTATE_M1_APSC_DIS BIT(22)
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#define CLUSTER_PSTATE_UNK_M2 BIT(22)
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#define CLUSTER_PSTATE_UNK_M1 BIT(20)
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#define CLUSTER_PSTATE_DESIRED2 GENMASK(15, 12)
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#define CLUSTER_PSTATE_APSC_BUSY BIT(7)
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#define CLUSTER_PSTATE_DESIRED1 GENMASK(4, 0)
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#define CLUSTER_SWITCH_TIMEOUT 100
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struct cluster_t {
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const char *name;
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u64 base;
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bool pcluster;
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uint32_t apsc_pstate;
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uint32_t default_pstate;
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};
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struct feat_t {
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const char *name;
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u64 offset;
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u64 clear;
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u64 set;
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u64 wait;
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bool pcluster_only;
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};
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static int set_pstate(const struct cluster_t *cluster, uint32_t pstate)
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{
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u64 val = read64(cluster->base + CLUSTER_PSTATE);
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if (FIELD_GET(CLUSTER_PSTATE_DESIRED1, val) != pstate) {
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val &= ~CLUSTER_PSTATE_DESIRED1;
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val |= CLUSTER_PSTATE_SET | FIELD_PREP(CLUSTER_PSTATE_DESIRED1, pstate);
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if (chip_id == T8103 || chip_id <= T6002) {
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val &= ~CLUSTER_PSTATE_DESIRED2;
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val |= CLUSTER_PSTATE_SET | FIELD_PREP(CLUSTER_PSTATE_DESIRED2, pstate);
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}
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write64(cluster->base + CLUSTER_PSTATE, val);
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if (poll32(cluster->base + CLUSTER_PSTATE, CLUSTER_PSTATE_BUSY, 0, CLUSTER_SWITCH_TIMEOUT) <
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0) {
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printf("cpufreq: Timed out waiting for cluster %s P-State switch\n", cluster->name);
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return -1;
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}
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}
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return 0;
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}
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int cpufreq_init_cluster(const struct cluster_t *cluster, const struct feat_t *features)
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{
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/* Reset P-State to the APSC p-state */
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if (cluster->apsc_pstate && set_pstate(cluster, cluster->apsc_pstate))
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return -1;
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/* CPU complex features */
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for (; features->name; features++) {
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if (features->pcluster_only && !cluster->pcluster)
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continue;
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u64 reg = cluster->base + features->offset;
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if (pmgr_get_feature(features->name))
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mask64(reg, features->clear, features->set);
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else
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mask64(reg, features->set, features->clear);
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if (features->wait && poll32(reg, features->wait, 0, CLUSTER_SWITCH_TIMEOUT) < 0) {
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printf("cpufreq: Timed out waiting for feature %s on cluster %s\n", features->name,
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cluster->name);
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return -1;
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}
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}
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/* Unknown */
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write64(cluster->base + 0x440f8, 1);
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/* Initialize APSC */
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set64(cluster->base + 0x200f8, BIT(40));
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switch (chip_id) {
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case T8103: {
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u64 lo = read64(cluster->base + 0x70000 + cluster->apsc_pstate * 0x20);
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u64 hi = read64(cluster->base + 0x70008 + cluster->apsc_pstate * 0x20);
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write64(cluster->base + 0x70210, lo);
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write64(cluster->base + 0x70218, hi);
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break;
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}
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case T8112: {
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u64 lo = read64(cluster->base + 0x78000 + cluster->apsc_pstate * 0x40);
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u64 hi = read64(cluster->base + 0x78008 + cluster->apsc_pstate * 0x40);
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write64(cluster->base + 0x7ffe8, lo);
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write64(cluster->base + 0x7fff0, hi);
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break;
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}
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}
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/* Default P-State */
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if (cluster->default_pstate && set_pstate(cluster, cluster->default_pstate))
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return -1;
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return 0;
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}
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void cpufreq_fixup_cluster(const struct cluster_t *cluster)
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{
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u64 val = read64(cluster->base + CLUSTER_PSTATE);
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// Older versions of m1n1 stage 1 erroneously cleared CLUSTER_PSTATE_UNK_Mx, so put it back for
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// firmwares it supported (don't touch anything newer, which includes newer devices).
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// Also clear the CLUSTER_PSTATE_DESIRED2 field since it doesn't seem to do anything, and isn't
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// used on newer chips.
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if (os_firmware.version != V_UNKNOWN && os_firmware.version <= V13_3) {
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u64 bits = 0;
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switch (chip_id) {
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case T8103:
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case T6000 ... T6002:
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bits = CLUSTER_PSTATE_UNK_M1;
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break;
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case T8112:
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case T6020 ... T6022:
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bits = CLUSTER_PSTATE_UNK_M2;
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break;
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default:
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return;
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}
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if (!(val & bits) || (val & CLUSTER_PSTATE_DESIRED2)) {
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val |= bits;
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val &= ~CLUSTER_PSTATE_DESIRED2;
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printf("cpufreq: Correcting setting for cluster %s\n", cluster->name);
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write64(cluster->base + CLUSTER_PSTATE, val);
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}
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}
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}
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static const struct cluster_t t8103_clusters[] = {
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{"ECPU", 0x210e00000, false, 1, 5},
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{"PCPU", 0x211e00000, true, 1, 7},
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{},
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};
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static const struct cluster_t t6000_clusters[] = {
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{"ECPU0", 0x210e00000, false, 1, 5},
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{"PCPU0", 0x211e00000, true, 1, 7},
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{"PCPU1", 0x212e00000, true, 1, 7},
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{},
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};
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static const struct cluster_t t6002_clusters[] = {
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{"ECPU0", 0x0210e00000, false, 1, 5},
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{"PCPU0", 0x0211e00000, true, 1, 7},
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{"PCPU1", 0x0212e00000, true, 1, 7},
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{"ECPU1", 0x2210e00000, false, 1, 5},
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{"PCPU2", 0x2211e00000, true, 1, 7},
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{"PCPU3", 0x2212e00000, true, 1, 7},
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{},
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};
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static const struct cluster_t t8112_clusters[] = {
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{"ECPU", 0x210e00000, false, 1, 7},
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{"PCPU", 0x211e00000, true, 1, 6},
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{},
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};
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static const struct cluster_t t6020_clusters[] = {
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{"ECPU0", 0x210e00000, false, 1, 5},
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{"PCPU0", 0x211e00000, true, 1, 6},
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{"PCPU1", 0x212e00000, true, 1, 6},
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{},
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};
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const struct cluster_t *cpufreq_get_clusters(void)
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{
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switch (chip_id) {
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case T8103:
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return t8103_clusters;
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case T6000:
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case T6001:
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return t6000_clusters;
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case T6002:
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return t6002_clusters;
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case T8112:
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return t8112_clusters;
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case T6020:
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case T6021:
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case T6022:
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return t6020_clusters;
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default:
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printf("cpufreq: Chip 0x%x is unsupported\n", chip_id);
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return NULL;
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}
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}
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static const struct feat_t t8103_features[] = {
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{"cpu-apsc", CLUSTER_PSTATE, CLUSTER_PSTATE_M1_APSC_DIS, 0, CLUSTER_PSTATE_APSC_BUSY, false},
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{"ppt-thrtl", 0x48400, 0, BIT(63), 0, false},
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{"llc-thrtl", 0x40240, 0, BIT(63), 0, false},
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{"amx-thrtl", 0x40250, 0, BIT(63), 0, false},
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{"cpu-fixed-freq-pll-relock", CLUSTER_PSTATE, 0, CLUSTER_PSTATE_FIXED_FREQ_PLL_RECLOCK, 0,
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false},
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{},
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};
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static const struct feat_t t8112_features[] = {
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{"cpu-apsc", CLUSTER_PSTATE, CLUSTER_PSTATE_M2_APSC_DIS, 0, CLUSTER_PSTATE_APSC_BUSY, false},
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{"ppt-thrtl", 0x40270, 0, BIT(63), 0, false},
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{"ppt-thrtl", 0x48408, 0, BIT(63), 0, false},
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{"ppt-thrtl", 0x48b30, 0, BIT(0), 0, true},
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{"ppt-thrtl", 0x20078, 0, BIT(0), 0, true},
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{"ppt-thrtl", 0x48400, 0, BIT(63), 0, false},
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{"amx-thrtl", 0x40250, 0, BIT(63), 0, false},
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{"cpu-fixed-freq-pll-relock", CLUSTER_PSTATE, 0, CLUSTER_PSTATE_FIXED_FREQ_PLL_RECLOCK, 0,
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false},
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{},
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};
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static const struct feat_t t6020_features[] = {
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{"cpu-apsc", CLUSTER_PSTATE, CLUSTER_PSTATE_M2_APSC_DIS, 0, CLUSTER_PSTATE_APSC_BUSY, false},
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{"ppt-thrtl", 0x48400, 0, BIT(63), 0, false},
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{"llc-thrtl", 0x40270, 0, BIT(63), 0, false},
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{"amx-thrtl", 0x40250, 0, BIT(63), 0, false},
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{"cpu-fixed-freq-pll-relock", CLUSTER_PSTATE, 0, CLUSTER_PSTATE_FIXED_FREQ_PLL_RECLOCK, 0,
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false},
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{},
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};
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const struct feat_t *cpufreq_get_features(void)
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{
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switch (chip_id) {
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case T8103:
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case T6000 ... T6002:
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return t8103_features;
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case T8112:
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return t8112_features;
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case T6020:
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case T6021:
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case T6022:
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return t6020_features;
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default:
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printf("cpufreq: Chip 0x%x is unsupported\n", chip_id);
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return NULL;
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}
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}
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int cpufreq_init(void)
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{
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printf("cpufreq: Initializing clusters\n");
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const struct cluster_t *cluster = cpufreq_get_clusters();
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const struct feat_t *features = cpufreq_get_features();
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if (!cluster || !features)
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return -1;
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bool err = false;
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while (cluster->base) {
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err |= cpufreq_init_cluster(cluster++, features);
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}
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return err ? -1 : 0;
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}
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void cpufreq_fixup(void)
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{
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const struct cluster_t *cluster = cpufreq_get_clusters();
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if (!cluster)
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return;
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while (cluster->base) {
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cpufreq_fixup_cluster(cluster++);
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}
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}
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