mirror of
https://github.com/AsahiLinux/m1n1
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175 lines
5.1 KiB
C
175 lines
5.1 KiB
C
/* SPDX-License-Identifier: MIT */
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#include "utils.h"
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#define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
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// HCR_EL2.E2H == 1
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#define CNTHCTL_EVNTIS BIT(17)
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#define CNTHCTL_EL1NVVCT BIT(16)
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#define CNTHCTL_EL1NVPCT BIT(15)
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#define CNTHCTL_EL1TVCT BIT(14)
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#define CNTHCTL_EL1TVT BIT(13)
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#define CNTHCTL_ECV BIT(12)
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#define CNTHCTL_EL1PTEN BIT(11)
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#define CNTHCTL_EL1PCTEN BIT(10)
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#define CNTHCTL_EL0PTEN BIT(9)
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#define CNTHCTL_EL0VTEN BIT(8)
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#define CNTHCTL_EVNTI GENMASK(7, 4)
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#define CNTHCTL_EVNTDIR BIT(3)
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#define CNTHCTL_EVNTEN BIT(2)
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#define CNTHCTL_EL0VCTEN BIT(1)
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#define CNTHCTL_EL0PCTEN BIT(0)
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#define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
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#define ESR_ISS2 GENMASK(36, 32)
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#define ESR_EC GENMASK(31, 26)
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#define ESR_IL BIT(25)
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#define ESR_ISS GENMASK(24, 0)
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#define ESR_EC_UNKNOWN 0b000000
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#define ESR_EC_WFI 0b000001
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#define ESR_EC_FP_TRAP 0b000111
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#define ESR_EC_PAUTH_TRAP 0b001000
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#define ESR_EC_LS64 0b001010
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#define ESR_EC_BTI 0b001101
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#define ESR_EC_ILLEGAL 0b001110
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#define ESR_EC_SVC 0b010101
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#define ESR_EC_HVC 0b010110
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#define ESR_EC_SMC 0b010111
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#define ESR_EC_MSR 0b011000
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#define ESR_EC_SVE 0b011001
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#define ESR_EC_PAUTH_FAIL 0b011100
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#define ESR_EC_IABORT_LOWER 0b100000
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#define ESR_EC_IABORT 0b100001
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#define ESR_EC_PC_ALIGN 0b100010
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#define ESR_EC_DABORT_LOWER 0b100100
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#define ESR_EC_DABORT 0b100101
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#define ESR_EC_SP_ALIGN 0b100110
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#define ESR_EC_FP_EXC 0b101100
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#define ESR_EC_SERROR 0b101111
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#define ESR_EC_BKPT_LOWER 0b110000
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#define ESR_EC_BKPT 0b110001
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#define ESR_EC_SSTEP_LOWER 0b110010
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#define ESR_EC_SSTEP 0b110011
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#define ESR_EC_WATCH_LOWER 0b110100
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#define ESR_EC_WATCH 0b110101
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#define ESR_EC_BRK 0b111100
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#define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
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#define HCR_TWEDEL GENMASK(63, 60)
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#define HCR_TWEDEn BIT(59)
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#define HCR_TID5 BIT(58)
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#define HCR_DCT BIT(57)
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#define HCR_ATA BIT(56)
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#define HCR_TTLBOS BIT(55)
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#define HCR_TTLBIS BIT(54)
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#define HCR_EnSCXT BIT(53)
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#define HCR_TOCU BIT(52)
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#define HCR_AMVOFFEN BIT(51)
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#define HCR_TICAB BIT(50)
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#define HCR_TID4 BIT(49)
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#define HCR_FIEN BIT(47)
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#define HCR_FWB BIT(46)
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#define HCR_NV2 BIT(45)
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#define HCR_AT BIT(44)
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#define HCR_NV1 BIT(43)
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#define HCR_NV1 BIT(43)
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#define HCR_NV BIT(42)
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#define HCR_NV BIT(42)
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#define HCR_API BIT(41)
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#define HCR_APK BIT(40)
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#define HCR_MIOCNCE BIT(38)
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#define HCR_TEA BIT(37)
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#define HCR_TERR BIT(36)
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#define HCR_TLOR BIT(35)
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#define HCR_E2H BIT(34)
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#define HCR_ID BIT(33)
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#define HCR_CD BIT(32)
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#define HCR_RW BIT(31)
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#define HCR_TRVM BIT(30)
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#define HCR_HCD BIT(29)
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#define HCR_TDZ BIT(28)
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#define HCR_TGE BIT(27)
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#define HCR_TVM BIT(26)
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#define HCR_TTLB BIT(25)
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#define HCR_TPU BIT(24)
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#define HCR_TPCP BIT(23)
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#define HCR_TPC BIT(23)
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#define HCR_TSW BIT(22)
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#define HCR_TACR BIT(21)
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#define HCR_TIDCP BIT(20)
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#define HCR_TSC BIT(19)
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#define HCR_TID3 BIT(18)
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#define HCR_TID2 BIT(17)
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#define HCR_TID1 BIT(16)
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#define HCR_TID0 BIT(15)
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#define HCR_TWE BIT(14)
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#define HCR_TWI BIT(13)
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#define HCR_DC BIT(12)
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#define HCR_BSU GENMASK(11, 10)
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#define HCR_FB BIT(9)
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#define HCR_VSE BIT(8)
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#define HCR_VI BIT(7)
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#define HCR_VF BIT(6)
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#define HCR_AMO BIT(5)
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#define HCR_IMO BIT(4)
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#define HCR_FMO BIT(3)
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#define HCR_PTW BIT(2)
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#define HCR_SWIO BIT(1)
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#define HCR_VM BIT(0)
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#define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
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// AArch64-PAR_EL1.F == 0b0
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#define PAR_ATTR GENMASK(63, 56)
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#define PAR_PA GENMASK(51, 12)
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#define PAR_NS BIT(9)
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#define PAR_SH GENMASK(8, 7)
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#define PAR_F BIT(0)
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// AArch64-PAR_EL1.F == 0b1
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#define PAR_S BIT(9)
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#define PAR_PTW BIT(8)
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#define PAR_FST GENMASK(6, 1)
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#define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
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#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
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#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
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// exception taken from AArch64
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#define SPSR_N BIT(31)
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#define SPSR_Z BIT(30)
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#define SPSR_C BIT(29)
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#define SPSR_V BIT(28)
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#define SPSR_TCO BIT(25)
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#define SPSR_DIT BIT(24)
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#define SPSR_UAO BIT(23)
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#define SPSR_PAN BIT(22)
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#define SPSR_SS BIT(21)
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#define SPSR_IL BIT(20)
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#define SPSR_SSBS BIT(12)
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#define SPSR_BTYPE GENMASK(11, 10)
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#define SPSR_D BIT(9)
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#define SPSR_A BIT(8)
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#define SPSR_I BIT(7)
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#define SPSR_F BIT(6)
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#define SPSR_M GENMASK(4, 0)
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#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
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// Profile(A)
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#define VTCR_SL2 BIT(33)
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#define VTCR_DS BIT(32)
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#define VTCR_NSA BIT(30)
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#define VTCR_NSW BIT(29)
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#define VTCR_HWU62 BIT(28)
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#define VTCR_HWU61 BIT(27)
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#define VTCR_HWU60 BIT(26)
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#define VTCR_HWU59 BIT(25)
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#define VTCR_HD BIT(22)
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#define VTCR_HA BIT(21)
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#define VTCR_VS BIT(19)
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#define VTCR_PS GENMASK(18, 16)
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#define VTCR_TG0 GENMASK(15, 14)
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#define VTCR_SH0 GENMASK(13, 12)
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#define VTCR_ORGN0 GENMASK(11, 10)
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#define VTCR_IRGN0 GENMASK(9, 8)
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#define VTCR_SL0 GENMASK(7, 6)
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#define VTCR_SL0 GENMASK(7, 6)
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#define VTCR_T0SZ GENMASK(5, 0)
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