mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-15 03:37:06 +00:00
d9561b7507
All the common/importable stuff now lives in the 'm1n1' module. General use tools are in tools/ Reverse engineering experiments are in experiments/ Signed-off-by: Hector Martin <marcan@marcan.st>
82 lines
2.4 KiB
Python
Executable file
82 lines
2.4 KiB
Python
Executable file
#!/usr/bin/env python3
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# SPDX-License-Identifier: MIT
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import sys, pathlib
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sys.path.append(str(pathlib.Path(__file__).resolve().parents[1]))
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from m1n1.setup import *
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from m1n1.find_regs import *
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from m1n1 import asm
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p.iodev_set_usage(IODEV.FB, 0)
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if u.mrs(SPRR_CONFIG_EL1):
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u.msr(GXF_CONFIG_EL12, 0)
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u.msr(SPRR_CONFIG_EL12, 0)
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u.msr(GXF_CONFIG_EL1, 0)
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u.msr(SPRR_CONFIG_EL1, 0)
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# Set up HCR_EL2 for EL1, since we can't do it after enabling GXF
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u.inst("nop", call="el1")
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all_regs = set()
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for reg in [SPRR_CONFIG_EL1, GXF_CONFIG_EL1, SPRR_CONFIG_EL12, GXF_CONFIG_EL12]:
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old_regs = set(find_regs(u, values=False))
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u.msr(reg, 1)
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el2_items = set(find_regs(u))
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el2_vals = dict(el2_items)
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new_regs = set(k for k, v in el2_items)
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all_regs = all_regs.union(new_regs)
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diff_regs = new_regs - old_regs
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print(reg)
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for r in sorted(diff_regs):
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print(" %s --> %lx" % (sysreg_name(r), u.mrs(r)))
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gl2_items = list(find_regs(u, regs=static_regs,call="gl2"))
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gl2_vals = dict(gl2_items)
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gl2_regs = set(k for k, v in gl2_items)
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print("GL2")
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for reg in sorted(gl2_regs - all_regs):
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print(" %s -> %lx" % (sysreg_name(reg), gl2_vals[reg]))
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for reg in sorted(gl2_regs):
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if reg in el2_vals and gl2_vals[reg] != el2_vals[reg]:
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print(" ! %s %lx -> %lx" % (sysreg_name(reg), el2_vals[reg], gl2_vals[reg]))
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u.msr(GXF_CONFIG_EL12, 0)
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u.msr(SPRR_CONFIG_EL12, 0)
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u.msr(GXF_CONFIG_EL1, 0)
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u.msr(SPRR_CONFIG_EL1, 0)
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gl1_items = list(find_regs(u, regs=static_regs, call="gl1"))
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gl1_vals = dict(gl1_items)
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gl1_regs = set(k for k, v in gl1_items)
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print("GL1")
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for reg in sorted(gl1_regs - all_regs):
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val = gl1_vals[reg]
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print(" %s -> %lx" % (sysreg_name(reg), val))
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cval = u.mrs(reg, call="gl1", silent=False)
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print(" cur: 0x%lx" % (cval))
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try:
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u.msr(reg, cval, call="gl1", silent=False)
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except:
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print(">RO")
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continue
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gl2_vals = dict(find_regs(u, regs=static_regs,call="gl2"))
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u.msr(reg, cval ^ 0xffff, call="gl1", silent=True)
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for r, v in find_regs(u, regs=static_regs, call="gl2"):
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if v != gl2_vals[r]:
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print(" GL2 access: %s %lx -> %lx" % (sysreg_name(r), gl2_vals[r], v))
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u.msr(reg, cval, call="gl1", silent=True)
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for reg in sorted(gl1_regs):
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if reg in el2_vals and gl1_vals[reg] != el2_vals[reg]:
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print(" ! %s %lx -> %lx" % (sysreg_name(reg), el2_vals[reg], gl1_vals[reg]))
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