mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-22 22:53:04 +00:00
446 lines
13 KiB
Python
446 lines
13 KiB
Python
import struct
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from construct import *
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from m1n1.utils import irange
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from m1n1.hw.dart import DART
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from m1n1.utils import chexdump
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from m1n1.proxyutils import RegMonitor
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from m1n1.constructutils import *
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from m1n1.trace.pcie import *
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PCIeDevTracer = PCIeDevTracer._reloadcls()
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mon = RegMonitor(hv.u)
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class WLANCfgSpace(PCICfgSpace):
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BAR0_WINDOW = 0x80, Register32
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WRAPPERBASE = 0x70, Register32
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INTSTATUS = 0x90, Register32
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INTMASK = 0x94, Register32
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SBMBX = 0x98, Register32
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LINK_STATUS_CTRL = 0xbc, Register32
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class WLANBAR0(RegMap):
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INTMASK = 0x2024, Register32
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MAILBOXINT = 0x2048, Register32
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MAILBOXMASK = 0x204c, Register32
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CONFIGADDR = 0x2120, Register32
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CONFIGDATA = 0x2124, Register32
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H2D_MAILBOX_0 = 0x2140, Register32
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H2D_MAILBOX_1 = 0x2144, Register32
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# Linux uses these, via offset 0 instead of 0x2000
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H2D_MAILBOX_0_ALT = 0x140, Register32
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H2D_MAILBOX_1_ALT = 0x144, Register32
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H2D_MAILBOX_0_64 = 0xa20, Register32
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H2D_MAILBOX_1_64 = 0xa24, Register32
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INTMASK_64 = 0xc14, Register32
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MAILBOXINT_64 = 0xc30, Register32
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MAILBOXMASK_64 = 0xc34, Register32
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class WLANSRAMEnd(RegMap):
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PAD = 0x00, Register32
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SHARED_BASE = 0x04, Register32
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class WLANSRAMShared(RegMap):
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FLAGS = 0, Register32
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CONSOLE_ADDR = 20, Register32
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FWID = 28, Register32
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MAX_RXBUFPOST = 34, Register16
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RX_DATAOFFSET = 36, Register32
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HTOD_MB_DATA_ADDR = 40, Register32
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DTOH_MB_DATA_ADDR = 44, Register32
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RING_INFO_ADDR = 48, Register32
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DMA_SCRATCH_LEN = 52, Register32
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DMA_SCRATCH_ADDR = 56, Register64
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HOST_SCB_ADDR = 64, Register64
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HOST_SCB_SIZE = 72, Register32
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BUZZ_DBG_PTR = 76, Register32
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FLAGS2 = 80, Register32
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HOST_CAP = 84, Register32
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HOST_TRAP_ADDR = 88, Register64
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DEVICE_FATAL_LOGBUF_START = 96, Register32
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HOFFLOAD_ADDR = 100, Register64
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FLAGS3 = 108, Register32
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HOST_CAP2 = 112, Register32
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HOST_CAP3 = 116, Register32
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class WLANSRAMRingInfo(RegMap):
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RINGMEM = 0x00, Register32
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H2D_W_IDX_PTR = 0x04, Register32
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H2D_R_IDX_PTR = 0x08, Register32
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D2H_W_IDX_PTR = 0x0c, Register32
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D2H_R_IDX_PTR = 0x10, Register32
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H2D_W_IDX_HOSTADDR = 0x14, Register64
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H2D_R_IDX_HOSTADDR = 0x1c, Register64
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D2H_W_IDX_HOSTADDR = 0x24, Register64
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D2H_R_IDX_HOSTADDR = 0x2c, Register64
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MAX_FLOWRINGS = 0x34, Register32
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MAX_SUBMISSIONRINGS = 0x38, Register32
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MAX_COMPLETIONRINGS = 0x3c, Register32
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COMMON_RING_CNT = 5
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class WLANSRAMRingMem(RegMap):
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MAX_ITEM = irange(0x04, COMMON_RING_CNT, 0x10), Register16
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LEN_ITEMS = irange(0x06, COMMON_RING_CNT, 0x10), Register16
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BASE_ADDR = irange(0x08, COMMON_RING_CNT, 0x10), Register32
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class MsgHeader(ConstructClass):
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subcon = Struct(
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"msg_type" / Int8ul,
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"if_id" / Int8sl,
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"flags" / Int8ul,
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"epoch" / Int8ul,
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"request_id" / Int32ul,
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)
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class ComplHeader(ConstructClass):
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subcon = Struct(
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"status" / Int16ul,
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"ring_id" / Int16ul,
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)
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class IOCtlPtrReq(ConstructClass):
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subcon = Struct(
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"cmd" / Int32ul,
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"trans_id" / Int16ul,
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"input_buf_len" / Int16ul,
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"output_buf_len" / Int16ul,
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"rsvd" / Array(3, Int16ul),
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"host_input_buf_addr" / Int64ul,
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)
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class IOCtlResp(ConstructClass):
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subcon = Struct(
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"compl" / ComplHeader,
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"resp_len" / Int16ul,
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"trans_id" / Int16ul,
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"cmd" / Int32ul,
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)
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class H2DMailboxData(ConstructClass):
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subcon = Struct(
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"data" / Int32ul
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)
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class D2HMailboxData(ConstructClass):
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subcon = Struct(
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"compl" / ComplHeader,
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"data" / Int32ul,
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)
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class RingMessage(ConstructClass):
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subcon = Struct(
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"hdr" / MsgHeader,
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"payload" / Switch(this.hdr.msg_type, {
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0x09: IOCtlPtrReq,
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0x0c: IOCtlResp,
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0x23: H2DMailboxData,
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0x24: D2HMailboxData,
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}, default=HexDump(GreedyBytes))
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)
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class RingState:
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pass
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class WLANRingTracer(PCIeDevTracer):
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def __init__(self, wlan, info):
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self.wlan = wlan
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self.hv = wlan.hv
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self.p = wlan.hv.p
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self.u = wlan.hv.u
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self.ringid = self.RX, self.PTR_IDX
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if self.ringid in wlan.state.rings:
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self.state = wlan.state.rings[self.ringid]
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else:
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self.state = wlan.state.rings[self.ringid] = RingState()
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self.state.rptr = 0
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self.info = info
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assert info.item_size == self.ITEM_SIZE
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self.base_addr = info.base_addr
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self.count = info.count
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if self.RX:
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d2h_paddr = self.wlan.iotranslate(self.wlan.state.d2h_w_idx_ha + 4 * self.PTR_IDX, 4)[0][0]
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assert d2h_paddr is not None
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self.hv.add_tracer(irange(d2h_paddr, 4), self.wlan.ident, TraceMode.SYNC,
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read=self.d2h_w_idx_readhook)
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def d2h_w_idx_readhook(self, evt):
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self.log("W idx read")
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self.poll()
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def poll(self):
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if self.RX:
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wptr = self.wlan.ioread(self.wlan.state.d2h_w_idx_ha + 4 * self.PTR_IDX, 4)
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else:
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wptr = self.wlan.ioread(self.wlan.state.h2d_w_idx_ha + 4 * self.PTR_IDX, 4)
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wptr = struct.unpack("<I", wptr)[0]
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while wptr != self.state.rptr:
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off = self.state.rptr * self.ITEM_SIZE
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addr = self.base_addr + off
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data = self.wlan.ioread(addr, self.ITEM_SIZE)
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self.pkt(data)
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self.state.rptr = (self.state.rptr + 1) % self.count
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def pkt(self, data):
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self.log("Got packet:")
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pkt = RingMessage.parse(data)
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self.log(pkt)
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if pkt.hdr.msg_type == 0x09:
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self.wlan.ioctlptr_req(pkt)
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if pkt.hdr.msg_type == 0x0c:
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self.wlan.ioctlresp(pkt)
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def log(self, msg):
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self.wlan.log(f"[{self.NAME}]{msg!s}")
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class WLANControlSubmitRingTracer(WLANRingTracer):
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NAME = "CTLSubmit"
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PTR_IDX = 0
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RX = False
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ITEM_SIZE = 0x28
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class WLANControlCompleteRingTracer(WLANRingTracer):
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NAME = "CTLCompl"
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PTR_IDX = 0
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RX = True
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ITEM_SIZE = 0x18
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class RingInfo:
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def __init__(self):
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self.count = None
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self.item_size = None
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self.base_addr = None
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def ready(self):
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return self.count is not None and self.item_size is not None and self.base_addr is not None
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class WLANTracer(PCIeDevTracer):
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DEFAULT_MODE = TraceMode.SYNC
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SRAM_BASE = 0x740000
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SRAM_SIZE = 0x1f9000
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BARMAPS = [WLANBAR0, None, None]
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CFGMAP = WLANCfgSpace
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RINGS = [
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WLANControlSubmitRingTracer,
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None, # RXPost
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WLANControlCompleteRingTracer,
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None, # TX complete
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None, # RX complete
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]
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CMDS = {
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1: "GET_VERSION",
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2: "UP",
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3: "DOWN",
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262: "GET_VAR",
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263: "SET_VAR",
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}
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def __init__(self, hv, apcie, bus, dev, fn, dart_path=None, verbose=False):
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super().__init__(hv, apcie, bus, dev, fn, verbose=verbose)
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self.u = hv.u
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self.p = hv.p
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self.dart_path = dart_path
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self.dart_dev = None
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self.dart = None
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self.rings = {}
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def init_state(self):
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super().init_state()
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self.state.shared_base = None
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self.state.ring_info_base = None
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self.state.ring_mem_base = None
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self.state.tcm_base = None
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self.state.tcm_size = None
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self.state.ring_info = None
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self.state.ring_mem = None
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self.state.ring_info_data = {}
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self.state.rings = {}
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self.state.ioctls = {}
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self.state.h2d_w_idx_ha = None
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self.state.h2d_r_idx_ha = None
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self.state.d2h_w_idx_ha = None
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self.state.d2h_r_idx_ha = None
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def config_dart(self):
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# Ugly...
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if self.dart_dev is None:
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for i in range (16):
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ttbr = self.dart.regs.TTBR[i, 0].reg
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if ttbr.VALID:
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self.log(f"DART device: {i}")
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self.dart_dev = i
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break
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else:
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raise Exception("Failed to find DART device")
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def ioread(self, addr, size):
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self.config_dart()
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return self.dart.ioread(self.dart_dev, addr, size)
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def iotranslate(self, addr, size):
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self.config_dart()
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return self.dart.iotranslate(self.dart_dev, addr, size)
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def r_SHARED_BASE(self, base):
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if base.value & 0xffff == (base.value >> 16) ^ 0xffff:
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return
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self.state.shared_base = base.value
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self.update_shared()
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def w_H2D_W_IDX_HOSTADDR(self, addr):
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self.state.h2d_w_idx_ha = addr.value
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def w_H2D_R_IDX_HOSTADDR(self, addr):
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self.state.h2d_r_idx_ha = addr.value
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def w_D2H_W_IDX_HOSTADDR(self, addr):
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self.state.d2h_w_idx_ha = addr.value
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def w_D2H_R_IDX_HOSTADDR(self, addr):
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self.state.d2h_r_idx_ha = addr.value
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def w_MAX_ITEM(self, val, index):
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info = self.state.ring_info_data.setdefault(index, RingInfo())
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info.count = val.value
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self.update_ring(index)
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def w_LEN_ITEMS(self, val, index):
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info = self.state.ring_info_data.setdefault(index, RingInfo())
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info.item_size = val.value
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self.update_ring(index)
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def w_BASE_ADDR(self, val, index):
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info = self.state.ring_info_data.setdefault(index, RingInfo())
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info.base_addr = val.value
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self.update_ring(index)
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def update_ring(self, idx):
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if idx not in self.state.ring_info_data:
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return
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info = self.state.ring_info_data[idx]
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if not info.ready():
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return
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if idx in self.rings:
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return
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if idx > len(self.RINGS):
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return
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ringcls = self.RINGS[idx]
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if ringcls is None:
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return
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self.rings[idx] = ringcls(self, info)
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def w_H2D_MAILBOX_0(self, val):
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ring = self.rings.get(2, None)
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if ring is not None:
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ring.poll()
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ring = self.rings.get(0, None)
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if ring is not None:
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ring.poll()
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w_H2D_MAILBOX_0_64 = w_H2D_MAILBOX_0
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w_H2D_MAILBOX_0_ALT = w_H2D_MAILBOX_0
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def ioctlptr_req(self, pkt):
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data = self.ioread(pkt.payload.host_input_buf_addr, pkt.payload.input_buf_len)
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cmd = self.CMDS.get(pkt.payload.cmd, "unk")
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self.log(f"IOCTL request ({cmd}):")
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chexdump(data, print_fn = self.log)
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self.state.ioctls[pkt.payload.trans_id] = pkt
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def ioctlresp(self, pkt):
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req = self.state.ioctls.get(pkt.payload.trans_id, None)
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if req is None:
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self.log(f"ERROR: unknown transaction ID {pkt.payload.trans_id:#x}")
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return
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data = self.ioread(req.payload.host_input_buf_addr, req.payload.output_buf_len)
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cmd = self.CMDS.get(pkt.payload.cmd, "unk")
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self.log(f"IOCTL response ({cmd}):")
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chexdump(data, print_fn = self.log)
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del self.state.ioctls[pkt.payload.trans_id]
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def trace_bar(self, idx, start, size):
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if idx != 2:
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return super().trace_bar(idx, start, size)
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self.state.tcm_base = start
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self.state.tcm_size = size
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self.update_tcm_tracers()
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def update_tcm_tracers(self):
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if self.state.tcm_base is None:
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return
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if self.dart is None:
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self.dart = DART.from_adt(self.u, self.dart_path)
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self.trace_regmap(self.state.tcm_base + self.SRAM_BASE + self.SRAM_SIZE - 8, 8,
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WLANSRAMEnd, name="sram")
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def update_shared(self):
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base = self.state.shared_base
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if base is None:
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return
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if self.state.ring_info_base is None:
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self.shared = WLANSRAMShared(self.hv.u, self.state.tcm_base + base)
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self.log("Reading shared info")
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self.shared.dump_regs()
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self.state.ring_info_base = self.shared.RING_INFO_ADDR.val
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if self.state.ring_mem_base is None:
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self.ring_info = WLANSRAMRingInfo(self.hv.u,
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self.state.tcm_base + self.state.ring_info_base)
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self.log("Reading ring info")
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self.ring_info.dump_regs()
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self.state.ring_mem_base = self.ring_info.RINGMEM.val
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self.trace_regmap(self.state.tcm_base + base, 0x100,
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WLANSRAMShared, name="shared")
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self.trace_regmap(self.state.tcm_base + self.state.ring_info_base, 0x40,
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WLANSRAMRingInfo, name="ringinfo")
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self.ring_mem = WLANSRAMRingMem(self.hv.u,
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self.state.tcm_base + self.state.ring_mem_base)
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self.log("Reading ring mem")
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self.ring_mem.dump_regs()
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self.trace_regmap(self.state.tcm_base + self.state.ring_mem_base,
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COMMON_RING_CNT * 0x10, WLANSRAMRingMem, name="ringmem")
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def start(self):
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super().start()
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self.update_tcm_tracers()
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self.update_shared()
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for i in range(len(self.RINGS)):
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self.update_ring(i)
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wlan_tracer = WLANTracer(hv, "/arm-io/apcie",
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4, 0, 0, "/arm-io/dart-apcie0")
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wlan_tracer.start()
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