mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-12-24 04:23:04 +00:00
1b1653dfe9
Signed-off-by: Hector Martin <marcan@marcan.st>
697 lines
21 KiB
C
697 lines
21 KiB
C
/* SPDX-License-Identifier: MIT */
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// #define DEBUG
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#include "hv.h"
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#include "assert.h"
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#include "cpu_regs.h"
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#include "iodev.h"
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#include "malloc.h"
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#include "string.h"
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#include "types.h"
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#include "uartproxy.h"
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#include "utils.h"
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#define PAGE_SIZE 0x4000
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#define CACHE_LINE_SIZE 64
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#define PTE_ACCESS BIT(10)
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#define PTE_SH_NS (0b11L << 8)
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#define PTE_S2AP_RW (0b11L << 6)
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#define PTE_MEMATTR_UNCHANGED (0b1111L << 2)
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#define PTE_ATTRIBUTES (PTE_ACCESS | PTE_SH_NS | PTE_S2AP_RW | PTE_MEMATTR_UNCHANGED)
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#define PTE_LOWER_ATTRIBUTES GENMASK(13, 2)
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#define PTE_VALID BIT(0)
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#define PTE_TYPE BIT(1)
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#define PTE_BLOCK 0
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#define PTE_TABLE 1
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#define PTE_PAGE 1
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#define VADDR_L4_INDEX_BITS 12
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#define VADDR_L3_INDEX_BITS 11
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#define VADDR_L2_INDEX_BITS 11
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#define VADDR_L4_OFFSET_BITS 2
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#define VADDR_L3_OFFSET_BITS 14
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#define VADDR_L2_OFFSET_BITS 25
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#define VADDR_BITS 36
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#define VADDR_L2_ALIGN_MASK GENMASK(VADDR_L2_OFFSET_BITS - 1, VADDR_L3_OFFSET_BITS)
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#define VADDR_L3_ALIGN_MASK GENMASK(VADDR_L3_OFFSET_BITS - 1, VADDR_L4_OFFSET_BITS)
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#define PTE_TARGET_MASK GENMASK(49, VADDR_L3_OFFSET_BITS)
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#define PTE_TARGET_MASK_L4 GENMASK(49, VADDR_L4_OFFSET_BITS)
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#define ENTRIES_PER_L2_TABLE BIT(VADDR_L2_INDEX_BITS)
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#define ENTRIES_PER_L3_TABLE BIT(VADDR_L3_INDEX_BITS)
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#define ENTRIES_PER_L4_TABLE BIT(VADDR_L4_INDEX_BITS)
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#define SPTE_TRACE_READ BIT(63)
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#define SPTE_TRACE_WRITE BIT(62)
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#define SPTE_SYNC_TRACE BIT(61)
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#define SPTE_TYPE GENMASK(52, 50)
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#define SPTE_MAP 0
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#define SPTE_HOOK 1
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#define SPTE_PROXY_HOOK_R 2
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#define SPTE_PROXY_HOOK_W 3
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#define SPTE_PROXY_HOOK_RW 4
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#define IS_HW(pte) ((pte) && pte & PTE_VALID)
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#define IS_SW(pte) ((pte) && !(pte & PTE_VALID))
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#define L2_IS_TABLE(pte) ((pte) && FIELD_GET(PTE_TYPE, pte) == PTE_TABLE)
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#define L2_IS_NOT_TABLE(pte) ((pte) && !L2_IS_TABLE(pte))
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#define L2_IS_HW_BLOCK(pte) (IS_HW(pte) && FIELD_GET(PTE_TYPE, pte) == PTE_BLOCK)
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#define L2_IS_SW_BLOCK(pte) \
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(IS_SW(pte) && FIELD_GET(PTE_TYPE, pte) == PTE_BLOCK && FIELD_GET(SPTE_TYPE, pte) == SPTE_MAP)
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#define L3_IS_TABLE(pte) (IS_SW(pte) && FIELD_GET(PTE_TYPE, pte) == PTE_TABLE)
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#define L3_IS_NOT_TABLE(pte) ((pte) && !L3_IS_TABLE(pte))
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#define L3_IS_HW_BLOCK(pte) (IS_HW(pte) && FIELD_GET(PTE_TYPE, pte) == PTE_PAGE)
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#define L3_IS_SW_BLOCK(pte) \
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(IS_SW(pte) && FIELD_GET(PTE_TYPE, pte) == PTE_BLOCK && FIELD_GET(SPTE_TYPE, pte) == SPTE_MAP)
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/*
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* We use 16KB page tables for stage 2 translation, and a 64GB (36-bit) guest
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* PA size, which results in the following virtual address space:
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*
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* [L2 index] [L3 index] [page offset]
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* 11 bits 11 bits 14 bits
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*
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* 32MB L2 mappings look like this:
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* [L2 index] [page offset]
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* 11 bits 25 bits
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*
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* We implement sub-page granularity mappings for software MMIO hooks, which behave
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* as an additional page table level used only by software. This works like this:
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*
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* [L2 index] [L3 index] [L4 index] [Word offset]
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* 11 bits 11 bits 12 bits 2 bits
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*
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* Thus, L4 sub-page tables are twice the size.
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*
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* We use invalid mappings (PTE_VALID == 0) to represent mmiotrace descriptors, but
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* otherwise the page table format is the same. The PTE_TYPE bit is weird, as 0 means
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* block but 1 means both table (at L<3) and page (at L3). For mmiotrace, this is
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* pushed to L4.
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*/
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static u64 hv_L2[ENTRIES_PER_L2_TABLE] ALIGNED(PAGE_SIZE);
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void hv_pt_init(void)
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{
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memset(hv_L2, 0, sizeof(hv_L2));
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msr(VTCR_EL2, FIELD_PREP(VTCR_PS, 1) | // 64GB PA size
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FIELD_PREP(VTCR_TG0, 2) | // 16KB page size
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FIELD_PREP(VTCR_SH0, 3) | // PTWs Inner Sharable
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FIELD_PREP(VTCR_ORGN0, 1) | // PTWs Cacheable
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FIELD_PREP(VTCR_IRGN0, 1) | // PTWs Cacheable
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FIELD_PREP(VTCR_SL0, 1) | // Start at level 2
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FIELD_PREP(VTCR_T0SZ, 28)); // 64GB translation region
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msr(VTTBR_EL2, hv_L2);
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}
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static void hv_pt_free_l3(u64 *l3)
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{
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if (!l3)
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return;
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for (u64 idx = 0; idx < ENTRIES_PER_L3_TABLE; idx++)
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if (IS_SW(l3[idx]) && FIELD_GET(PTE_TYPE, l3[idx]) == PTE_TABLE)
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free((void *)(l3[idx] & PTE_TARGET_MASK));
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free(l3);
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}
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static void hv_pt_map_l2(u64 from, u64 to, u64 size, u64 incr)
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{
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assert((from & MASK(VADDR_L2_OFFSET_BITS)) == 0);
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assert(IS_SW(to) || (to & PTE_TARGET_MASK & MASK(VADDR_L2_OFFSET_BITS)) == 0);
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assert((size & MASK(VADDR_L2_OFFSET_BITS)) == 0);
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to |= FIELD_PREP(PTE_TYPE, PTE_BLOCK);
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for (; size; size -= BIT(VADDR_L2_OFFSET_BITS)) {
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u64 idx = from >> VADDR_L2_OFFSET_BITS;
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if (L2_IS_TABLE(hv_L2[idx]))
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hv_pt_free_l3((u64 *)(hv_L2[idx] & PTE_TARGET_MASK));
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hv_L2[idx] = to;
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from += BIT(VADDR_L2_OFFSET_BITS);
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to += incr * BIT(VADDR_L2_OFFSET_BITS);
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}
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}
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static u64 *hv_pt_get_l3(u64 from)
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{
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u64 l2idx = from >> VADDR_L2_OFFSET_BITS;
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u64 l2d = hv_L2[l2idx];
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if (L2_IS_TABLE(l2d))
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return (u64 *)(l2d & PTE_TARGET_MASK);
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u64 *l3 = (u64 *)memalign(PAGE_SIZE, ENTRIES_PER_L3_TABLE * sizeof(u64));
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if (l2d) {
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u64 incr = 0;
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u64 l3d = l2d;
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if (IS_HW(l2d)) {
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l3d &= ~PTE_TYPE;
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l3d |= FIELD_PREP(PTE_TYPE, PTE_PAGE);
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incr = BIT(VADDR_L3_OFFSET_BITS);
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} else if (IS_SW(l2d) && FIELD_GET(SPTE_TYPE, l3d) == SPTE_MAP) {
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incr = BIT(VADDR_L3_OFFSET_BITS);
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}
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for (u64 idx = 0; idx < ENTRIES_PER_L3_TABLE; idx++, l3d += incr)
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l3[idx] = l3d;
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} else {
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memset64(l3, 0, ENTRIES_PER_L3_TABLE * sizeof(u64));
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}
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l2d = ((u64)l3) | FIELD_PREP(PTE_TYPE, PTE_TABLE) | PTE_VALID;
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hv_L2[l2idx] = l2d;
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return l3;
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}
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static void hv_pt_map_l3(u64 from, u64 to, u64 size, u64 incr)
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{
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assert((from & MASK(VADDR_L3_OFFSET_BITS)) == 0);
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assert(IS_SW(to) || (to & PTE_TARGET_MASK & MASK(VADDR_L3_OFFSET_BITS)) == 0);
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assert((size & MASK(VADDR_L3_OFFSET_BITS)) == 0);
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if (IS_HW(to))
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to |= FIELD_PREP(PTE_TYPE, PTE_PAGE);
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else
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to |= FIELD_PREP(PTE_TYPE, PTE_BLOCK);
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for (; size; size -= BIT(VADDR_L3_OFFSET_BITS)) {
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u64 idx = (from >> VADDR_L3_OFFSET_BITS) & MASK(VADDR_L3_INDEX_BITS);
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u64 *l3 = hv_pt_get_l3(from);
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if (L3_IS_TABLE(l3[idx]))
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free((void *)(l3[idx] & PTE_TARGET_MASK));
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l3[idx] = to;
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from += BIT(VADDR_L3_OFFSET_BITS);
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to += incr * BIT(VADDR_L3_OFFSET_BITS);
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}
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}
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static u64 *hv_pt_get_l4(u64 from)
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{
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u64 *l3 = hv_pt_get_l3(from);
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u64 l3idx = (from >> VADDR_L3_OFFSET_BITS) & MASK(VADDR_L3_INDEX_BITS);
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u64 l3d = l3[l3idx];
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if (L3_IS_TABLE(l3d)) {
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return (u64 *)(l3d & PTE_TARGET_MASK);
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}
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if (IS_HW(l3d)) {
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assert(FIELD_GET(PTE_TYPE, l3d) == PTE_PAGE);
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l3d &= PTE_TARGET_MASK;
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l3d |= FIELD_PREP(PTE_TYPE, PTE_BLOCK) | FIELD_PREP(SPTE_TYPE, SPTE_MAP);
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}
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u64 *l4 = (u64 *)memalign(PAGE_SIZE, ENTRIES_PER_L4_TABLE * sizeof(u64));
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if (l3d) {
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u64 incr = 0;
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u64 l4d = l3d;
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l4d &= ~PTE_TYPE;
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l4d |= FIELD_PREP(PTE_TYPE, PTE_PAGE);
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if (FIELD_GET(SPTE_TYPE, l4d) == SPTE_MAP)
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incr = BIT(VADDR_L4_OFFSET_BITS);
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for (u64 idx = 0; idx < ENTRIES_PER_L4_TABLE; idx++, l4d += incr)
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l4[idx] = l4d;
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} else {
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memset64(l4, 0, ENTRIES_PER_L4_TABLE * sizeof(u64));
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}
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l3d = ((u64)l4) | FIELD_PREP(PTE_TYPE, PTE_TABLE);
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l3[l3idx] = l3d;
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return l4;
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}
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static void hv_pt_map_l4(u64 from, u64 to, u64 size, u64 incr)
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{
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assert((from & MASK(VADDR_L4_OFFSET_BITS)) == 0);
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assert((size & MASK(VADDR_L4_OFFSET_BITS)) == 0);
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assert(!IS_HW(to));
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if (IS_SW(to))
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to |= FIELD_PREP(PTE_TYPE, PTE_PAGE);
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for (; size; size -= BIT(VADDR_L4_OFFSET_BITS)) {
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u64 idx = (from >> VADDR_L4_OFFSET_BITS) & MASK(VADDR_L4_INDEX_BITS);
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u64 *l4 = hv_pt_get_l4(from);
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l4[idx] = to;
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from += BIT(VADDR_L4_OFFSET_BITS);
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to += incr * BIT(VADDR_L4_OFFSET_BITS);
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}
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}
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int hv_map(u64 from, u64 to, u64 size, u64 incr)
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{
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u64 chunk;
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bool hw = IS_HW(to);
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if (from & MASK(VADDR_L4_OFFSET_BITS) || size & MASK(VADDR_L4_OFFSET_BITS))
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return -1;
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if (hw && (from & MASK(VADDR_L3_OFFSET_BITS) || size & MASK(VADDR_L3_OFFSET_BITS))) {
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printf("HV: cannot use L4 pages with HW mappings (0x%lx -> 0x%lx)\n", from, to);
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return -1;
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}
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// L4 mappings to boundary
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chunk = min(size, ALIGN_UP(from, MASK(VADDR_L3_OFFSET_BITS)) - from);
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if (chunk) {
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assert(!hw);
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hv_pt_map_l4(from, to, chunk, incr);
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from += chunk;
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to += incr * chunk;
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size -= chunk;
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}
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// L3 mappings to boundary
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chunk = ALIGN_DOWN(min(size, ALIGN_UP(from, MASK(VADDR_L2_OFFSET_BITS)) - from),
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MASK(VADDR_L3_OFFSET_BITS));
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if (chunk) {
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hv_pt_map_l3(from, to, chunk, incr);
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from += chunk;
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to += incr * chunk;
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size -= chunk;
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}
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// L2 mappings
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chunk = ALIGN_DOWN(size, MASK(VADDR_L2_OFFSET_BITS));
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if (chunk && (!hw || (to & VADDR_L2_ALIGN_MASK) == 0)) {
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hv_pt_map_l2(from, to, chunk, incr);
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from += chunk;
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to += incr * chunk;
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size -= chunk;
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}
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// L3 mappings to end
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chunk = ALIGN_DOWN(size, MASK(VADDR_L3_OFFSET_BITS));
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if (chunk) {
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hv_pt_map_l3(from, to, chunk, incr);
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from += chunk;
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to += incr * chunk;
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size -= chunk;
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}
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// L4 mappings to end
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if (size) {
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assert(!hw);
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hv_pt_map_l4(from, to, size, incr);
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}
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return 0;
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}
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int hv_unmap(u64 from, u64 size)
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{
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return hv_map(from, 0, size, 0);
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}
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int hv_map_hw(u64 from, u64 to, u64 size)
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{
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return hv_map(from, to | PTE_ATTRIBUTES | PTE_VALID, size, 1);
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}
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int hv_map_sw(u64 from, u64 to, u64 size)
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{
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return hv_map(from, to | FIELD_PREP(SPTE_TYPE, SPTE_MAP), size, 1);
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}
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int hv_map_hook(u64 from, hv_hook_t *hook, u64 size)
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{
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return hv_map(from, ((u64)hook) | FIELD_PREP(SPTE_TYPE, SPTE_HOOK), size, 0);
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}
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int hv_map_proxy_hook(u64 from, u64 id, u64 size)
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{
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return hv_map(from, FIELD_PREP(PTE_TARGET_MASK_L4, id) | FIELD_PREP(SPTE_TYPE, SPTE_HOOK), size,
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0);
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}
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u64 hv_translate(u64 addr, bool s1, bool w)
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{
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if (!(mrs(SCTLR_EL12) & SCTLR_M))
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return addr; // MMU off
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u64 el = FIELD_GET(SPSR_M, mrs(SPSR_EL2)) >> 2;
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u64 save = mrs(PAR_EL1);
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if (w) {
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if (s1) {
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if (el == 0)
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asm("at s1e0w, %0" : : "r"(addr));
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else
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asm("at s1e1w, %0" : : "r"(addr));
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} else {
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if (el == 0)
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asm("at s12e0w, %0" : : "r"(addr));
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else
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asm("at s12e1w, %0" : : "r"(addr));
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}
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} else {
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if (s1) {
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if (el == 0)
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asm("at s1e0r, %0" : : "r"(addr));
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else
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asm("at s1e1r, %0" : : "r"(addr));
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} else {
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if (el == 0)
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asm("at s12e0r, %0" : : "r"(addr));
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else
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asm("at s12e1r, %0" : : "r"(addr));
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}
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}
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u64 par = mrs(PAR_EL1);
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msr(PAR_EL1, save);
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if (par & PAR_F) {
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dprintf("hv_translate(0x%lx, %d, %d): fault 0x%lx\n", addr, s1, w, par);
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return 0; // fault
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} else {
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return (par & PAR_PA) | (addr & 0xfff);
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}
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}
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u64 hv_pt_walk(u64 addr)
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{
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dprintf("hv_pt_walk(0x%lx)\n", addr);
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u64 idx = addr >> VADDR_L2_OFFSET_BITS;
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u64 l2d = hv_L2[idx];
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dprintf(" l2d = 0x%lx\n", l2d);
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if (!L2_IS_TABLE(l2d)) {
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if (L2_IS_SW_BLOCK(l2d) || L2_IS_HW_BLOCK(l2d))
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l2d |= addr & (VADDR_L2_ALIGN_MASK | VADDR_L3_ALIGN_MASK);
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dprintf(" result: 0x%lx\n", l2d);
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return l2d;
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}
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idx = (addr >> VADDR_L3_OFFSET_BITS) & MASK(VADDR_L3_INDEX_BITS);
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u64 l3d = ((u64 *)(l2d & PTE_TARGET_MASK))[idx];
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dprintf(" l3d = 0x%lx\n", l3d);
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if (!L3_IS_TABLE(l3d)) {
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if (L3_IS_SW_BLOCK(l3d))
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l3d |= addr & VADDR_L3_ALIGN_MASK;
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if (L3_IS_HW_BLOCK(l3d)) {
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l3d &= ~PTE_LOWER_ATTRIBUTES;
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l3d |= addr & VADDR_L3_ALIGN_MASK;
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}
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dprintf(" result: 0x%lx\n", l3d);
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return l3d;
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}
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idx = (addr >> VADDR_L4_OFFSET_BITS) & MASK(VADDR_L4_INDEX_BITS);
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dprintf(" l4 idx = 0x%lx\n", idx);
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u64 l4d = ((u64 *)(l3d & PTE_TARGET_MASK))[idx];
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dprintf(" l4d = 0x%lx\n", l4d);
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return l4d;
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}
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#define CHECK_RN \
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if (Rn == 31) \
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goto bail
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#define DECODE_OK \
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if (!val) \
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return true
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#define EXT(n, b) (((s32)(((u32)(n)) << (32 - (b)))) >> (32 - (b)))
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static bool emulate_load(u64 *regs, u32 insn, u64 *val, u64 *width)
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{
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u64 Rt = insn & 0x1f;
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u64 Rn = (insn >> 5) & 0x1f;
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u64 imm9 = EXT((insn >> 12) & 0x1ff, 9);
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*width = insn >> 30;
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if (val)
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dprintf("emulate_load(%p, 0x%08x, 0x%08lx, %ld\n", regs, insn, *val, *width);
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if ((insn & 0x3fe00400) == 0x38400400) {
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// LDRx (immediate) Pre/Post-index
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CHECK_RN;
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DECODE_OK;
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regs[Rn] += imm9;
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regs[Rt] = *val;
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} else if ((insn & 0x3fc00000) == 0x39400000) {
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// LDRx (immediate) Unsigned offset
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DECODE_OK;
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regs[Rt] = *val;
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} else if ((insn & 0x3fa00400) == 0x38800400) {
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// LDRSx (immediate) Pre/Post-index
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CHECK_RN;
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DECODE_OK;
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regs[Rn] += imm9;
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regs[Rt] = EXT(*val, 8 << *width);
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} else if ((insn & 0x3fa00000) == 0x39800000) {
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// LDRSx (immediate) Unsigned offset
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DECODE_OK;
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regs[Rt] = EXT(*val, 8 << *width);
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} else if ((insn & 0x3fe04c00) == 0x38604800) {
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// LDRx (register)
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DECODE_OK;
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regs[Rt] = *val;
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} else if ((insn & 0x3fa04c00) == 0x38a04800) {
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// LDRSx (register)
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DECODE_OK;
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regs[Rt] = EXT(*val, 8 << *width);
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} else {
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goto bail;
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}
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return true;
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bail:
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printf("HV: load not emulated: 0x%08x\n", insn);
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return false;
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}
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static bool emulate_store(u64 *regs, u32 insn, u64 *val, u64 *width)
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{
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u64 Rt = insn & 0x1f;
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u64 Rn = (insn >> 5) & 0x1f;
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u64 imm9 = EXT((insn >> 12) & 0x1ff, 9);
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*width = insn >> 30;
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dprintf("emulate_store(%p, 0x%08x, ..., %ld) = ", regs, insn, *width);
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regs[31] = 0;
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if ((insn & 0x3fe00400) == 0x38000400) {
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// STRx (immediate) Pre/Post-index
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CHECK_RN;
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regs[Rn] += imm9;
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*val = regs[Rt];
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} else if ((insn & 0x3fc00000) == 0x39000000) {
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// STRx (immediate) Unsigned offset
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*val = regs[Rt];
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} else if ((insn & 0x3fe04c00) == 0x38204800) {
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// STRx (register)
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*val = regs[Rt];
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} else {
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goto bail;
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}
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dprintf("0x%lx\n", *width);
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return true;
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bail:
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printf("HV: store not emulated: 0x%08x\n", insn);
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return false;
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}
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bool hv_handle_dabort(u64 *regs)
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{
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u64 esr = mrs(ESR_EL2);
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u64 far = mrs(FAR_EL2);
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u64 ipa = hv_translate(far, true, esr & ESR_ISS_DABORT_WnR);
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dprintf("hv_handle_abort(): stage 1 0x%0lx -> 0x%lx\n", far, ipa);
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if (!ipa) {
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printf("HV: stage 1 translation failed at VA 0x%0lx\n", far);
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return false;
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}
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if (ipa >= BIT(VADDR_BITS)) {
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printf("hv_handle_abort(): IPA out of bounds: 0x%0lx -> 0x%lx\n", far, ipa);
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return false;
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}
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u64 pte = hv_pt_walk(ipa);
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if (!pte) {
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printf("HV: Unmapped IPA 0x%lx\n", ipa);
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return false;
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}
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if (IS_HW(pte)) {
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printf("HV: Data abort on mapped page (0x%lx -> 0x%lx)\n", far, pte);
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return false;
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}
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assert(IS_SW(pte));
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u64 target = pte & PTE_TARGET_MASK_L4;
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u64 paddr = target | (far & MASK(VADDR_L4_OFFSET_BITS));
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u64 elr = mrs(ELR_EL2);
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u64 elr_pa = hv_translate(elr, false, false);
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if (!elr_pa) {
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printf("HV: Failed to fetch instruction for data abort at 0x%lx\n", elr);
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return false;
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}
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u32 insn = read32(elr_pa);
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u64 val = 0;
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u64 width;
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if (esr & ESR_ISS_DABORT_WnR) {
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if (!emulate_store(regs, insn, &val, &width))
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return false;
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if (pte & SPTE_TRACE_WRITE) {
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struct hv_evt_mmiotrace evt = {
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.flags = FIELD_PREP(MMIO_EVT_WIDTH, width) | MMIO_EVT_WRITE,
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.pc = elr,
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.addr = ipa,
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.data = val,
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};
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uartproxy_send_event(EVT_MMIOTRACE, &evt, sizeof(evt));
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if (pte & SPTE_SYNC_TRACE)
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iodev_flush(uartproxy_iodev);
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}
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switch (FIELD_GET(SPTE_TYPE, pte)) {
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case SPTE_PROXY_HOOK_R:
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paddr = ipa;
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// fallthrough
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case SPTE_MAP:
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dprintf("HV: SPTE_MAP[W] @0x%lx 0x%lx -> 0x%lx (w=%d): 0x%lx\n", elr_pa, far, paddr,
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1 << width, val);
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switch (width) {
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case SAS_8B:
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write8(paddr, val);
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break;
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case SAS_16B:
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write16(paddr, val);
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break;
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case SAS_32B:
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write32(paddr, val);
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break;
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case SAS_64B:
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write64(paddr, val);
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break;
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}
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break;
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case SPTE_HOOK: {
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hv_hook_t *hook = (hv_hook_t *)target;
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if (!hook(ipa, &val, true, width))
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return false;
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dprintf("HV: SPTE_HOOK[W] @0x%lx 0x%lx -> 0x%lx (w=%d) @%p: 0x%lx\n", elr_pa, far,
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ipa, 1 << width, hook, val);
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break;
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}
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case SPTE_PROXY_HOOK_RW:
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case SPTE_PROXY_HOOK_W: {
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struct hv_vm_proxy_hook_data hook = {
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.flags = FIELD_PREP(MMIO_EVT_WIDTH, width) | MMIO_EVT_WRITE,
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.id = FIELD_GET(PTE_TARGET_MASK_L4, pte),
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.addr = ipa,
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.data = val,
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};
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hv_exc_proxy(regs, START_HV, HV_HOOK_VM, &hook);
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break;
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}
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default:
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printf("HV: invalid SPTE 0x%016lx for IPA 0x%lx\n", pte, ipa);
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return false;
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}
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} else {
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if (!emulate_load(regs, insn, NULL, &width))
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return false;
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switch (FIELD_GET(SPTE_TYPE, pte)) {
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case SPTE_PROXY_HOOK_W:
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paddr = ipa;
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// fallthrough
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case SPTE_MAP:
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switch (width) {
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case SAS_8B:
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val = read8(paddr);
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break;
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case SAS_16B:
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val = read16(paddr);
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break;
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case SAS_32B:
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val = read32(paddr);
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break;
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case SAS_64B:
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val = read64(paddr);
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break;
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}
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dprintf("HV: SPTE_MAP[R] @0x%lx 0x%lx -> 0x%lx (w=%d): 0x%lx\n", elr_pa, far, paddr,
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1 << width, val);
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break;
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case SPTE_HOOK:
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val = 0;
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hv_hook_t *hook = (hv_hook_t *)target;
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if (!hook(ipa, &val, false, width))
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return false;
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dprintf("HV: SPTE_HOOK[R] @0x%lx 0x%lx -> 0x%lx (w=%d) @%p: 0x%lx\n", elr_pa, far,
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ipa, 1 << width, hook, val);
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break;
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case SPTE_PROXY_HOOK_RW:
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case SPTE_PROXY_HOOK_R: {
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struct hv_vm_proxy_hook_data hook = {
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.flags = FIELD_PREP(MMIO_EVT_WIDTH, width),
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.id = FIELD_GET(PTE_TARGET_MASK_L4, pte),
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.addr = ipa,
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};
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hv_exc_proxy(regs, START_HV, HV_HOOK_VM, &hook);
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val = hook.data;
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break;
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}
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default:
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printf("HV: invalid SPTE 0x%016lx for IPA 0x%lx\n", pte, ipa);
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return false;
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}
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if (pte & SPTE_TRACE_READ) {
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struct hv_evt_mmiotrace evt = {
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.flags = FIELD_PREP(MMIO_EVT_WIDTH, width),
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.pc = elr,
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.addr = ipa,
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.data = val,
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};
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uartproxy_send_event(EVT_MMIOTRACE, &evt, sizeof(evt));
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if (pte & SPTE_SYNC_TRACE)
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iodev_flush(uartproxy_iodev);
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}
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if (!emulate_load(regs, insn, &val, &width))
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return false;
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}
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return true;
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}
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