mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-12-19 02:03:06 +00:00
1ac6c7659d
PMGR cpustart offset moved... Signed-off-by: Hector Martin <marcan@marcan.st>
296 lines
6.4 KiB
C
296 lines
6.4 KiB
C
/* SPDX-License-Identifier: MIT */
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#include "smp.h"
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#include "adt.h"
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#include "cpu_regs.h"
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#include "malloc.h"
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#include "pmgr.h"
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#include "soc.h"
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#include "string.h"
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#include "types.h"
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#include "utils.h"
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#define CPU_START_OFF_T8103 0x54000
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#define CPU_START_OFF_T8112 0x34000
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#define CPU_REG_CORE GENMASK(7, 0)
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#define CPU_REG_CLUSTER GENMASK(10, 8)
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#define CPU_REG_DIE GENMASK(14, 11)
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struct spin_table {
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u64 mpidr;
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u64 flag;
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u64 target;
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u64 args[4];
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u64 retval;
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};
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void *_reset_stack;
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#define DUMMY_STACK_SIZE 0x1000
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u8 dummy_stack[DUMMY_STACK_SIZE];
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u8 *secondary_stacks[MAX_CPUS] = {dummy_stack};
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static bool wfe_mode = false;
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static int target_cpu;
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static struct spin_table spin_table[MAX_CPUS];
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extern u8 _vectors_start[0];
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void smp_secondary_entry(void)
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{
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struct spin_table *me = &spin_table[target_cpu];
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if (in_el2())
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msr(TPIDR_EL2, target_cpu);
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else
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msr(TPIDR_EL1, target_cpu);
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printf(" Index: %d (table: %p)\n\n", target_cpu, me);
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me->mpidr = mrs(MPIDR_EL1) & 0xFFFFFF;
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sysop("dmb sy");
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me->flag = 1;
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sysop("dmb sy");
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u64 target;
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while (1) {
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while (!(target = me->target)) {
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if (wfe_mode) {
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sysop("wfe");
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} else {
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deep_wfi();
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msr(SYS_IMP_APL_IPI_SR_EL1, 1);
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}
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sysop("isb");
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}
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sysop("dmb sy");
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me->flag++;
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sysop("dmb sy");
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me->retval = ((u64(*)(u64 a, u64 b, u64 c, u64 d))target)(me->args[0], me->args[1],
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me->args[2], me->args[3]);
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sysop("dmb sy");
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me->target = 0;
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sysop("dmb sy");
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}
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}
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static void smp_start_cpu(int index, int die, int cluster, int core, u64 rvbar, u64 cpu_start_base)
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{
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int i;
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if (index >= MAX_CPUS)
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return;
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if (spin_table[index].flag)
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return;
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printf("Starting CPU %d (%d:%d:%d)... ", index, die, cluster, core);
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memset(&spin_table[index], 0, sizeof(struct spin_table));
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target_cpu = index;
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secondary_stacks[index] = memalign(0x4000, SECONDARY_STACK_SIZE);
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_reset_stack = secondary_stacks[index] + SECONDARY_STACK_SIZE;
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sysop("dmb sy");
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write64(rvbar, (u64)_vectors_start);
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cpu_start_base += die * PMGR_DIE_OFFSET;
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// Some kind of system level startup/status bit
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// Without this, IRQs don't work
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write32(cpu_start_base + 0x4, 1 << (4 * cluster + core));
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// Actually start the core
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write32(cpu_start_base + 0x8 + 4 * cluster, 1 << core);
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for (i = 0; i < 500; i++) {
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sysop("dmb ld");
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if (spin_table[index].flag)
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break;
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udelay(1000);
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}
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if (i >= 500)
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printf("Failed!\n");
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else
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printf(" Started.\n");
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_reset_stack = dummy_stack + DUMMY_STACK_SIZE;
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}
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void smp_start_secondaries(void)
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{
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printf("Starting secondary CPUs...\n");
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int pmgr_path[8];
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u64 pmgr_reg;
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if (adt_path_offset_trace(adt, "/arm-io/pmgr", pmgr_path) < 0) {
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printf("Error getting /arm-io/pmgr node\n");
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return;
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}
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if (adt_get_reg(adt, pmgr_path, "reg", 0, &pmgr_reg, NULL) < 0) {
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printf("Error getting /arm-io/pmgr regs\n");
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return;
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}
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int node = adt_path_offset(adt, "/cpus");
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if (node < 0) {
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printf("Error getting /cpus node\n");
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return;
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}
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int cpu_nodes[MAX_CPUS];
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u64 cpu_start_off;
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memset(cpu_nodes, 0, sizeof(cpu_nodes));
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switch (chip_id) {
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case T8103:
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case T6000:
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case T6001:
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case T6002:
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cpu_start_off = CPU_START_OFF_T8103;
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break;
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case T8112:
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cpu_start_off = CPU_START_OFF_T8112;
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break;
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default:
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printf("CPU start offset is unknown for this SoC!\n");
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return;
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}
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ADT_FOREACH_CHILD(adt, node)
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{
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u32 cpu_id;
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if (ADT_GETPROP(adt, node, "cpu-id", &cpu_id) < 0)
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continue;
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if (cpu_id >= MAX_CPUS) {
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printf("cpu-id %d exceeds max CPU count %d: increase MAX_CPUS\n", cpu_id, MAX_CPUS);
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continue;
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}
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cpu_nodes[cpu_id] = node;
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}
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for (int i = 1; i < MAX_CPUS; i++) {
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int node = cpu_nodes[i];
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if (!node)
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continue;
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u32 reg;
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u64 cpu_impl_reg[2];
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if (ADT_GETPROP(adt, node, "reg", ®) < 0)
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continue;
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if (ADT_GETPROP_ARRAY(adt, node, "cpu-impl-reg", cpu_impl_reg) < 0)
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continue;
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u8 core = FIELD_GET(CPU_REG_CORE, reg);
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u8 cluster = FIELD_GET(CPU_REG_CLUSTER, reg);
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u8 die = FIELD_GET(CPU_REG_DIE, reg);
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smp_start_cpu(i, die, cluster, core, cpu_impl_reg[0], pmgr_reg + cpu_start_off);
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}
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spin_table[0].mpidr = mrs(MPIDR_EL1) & 0xFFFFFF;
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}
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void smp_send_ipi(int cpu)
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{
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if (cpu >= MAX_CPUS)
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return;
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u64 mpidr = spin_table[cpu].mpidr;
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msr(SYS_IMP_APL_IPI_RR_GLOBAL_EL1, (mpidr & 0xff) | ((mpidr & 0xff00) << 8));
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}
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void smp_call4(int cpu, void *func, u64 arg0, u64 arg1, u64 arg2, u64 arg3)
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{
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if (cpu >= MAX_CPUS)
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return;
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struct spin_table *target = &spin_table[cpu];
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if (cpu == 0)
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return;
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u64 flag = target->flag;
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target->args[0] = arg0;
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target->args[1] = arg1;
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target->args[2] = arg2;
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target->args[3] = arg3;
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sysop("dmb sy");
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target->target = (u64)func;
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sysop("dsb sy");
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if (wfe_mode)
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sysop("sev");
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else
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smp_send_ipi(cpu);
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while (target->flag == flag)
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sysop("dmb sy");
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}
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u64 smp_wait(int cpu)
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{
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if (cpu >= MAX_CPUS)
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return 0;
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struct spin_table *target = &spin_table[cpu];
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while (target->target)
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sysop("dmb sy");
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return target->retval;
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}
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void smp_set_wfe_mode(bool new_mode)
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{
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wfe_mode = new_mode;
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sysop("dsb sy");
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for (int cpu = 1; cpu < MAX_CPUS; cpu++)
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if (smp_is_alive(cpu))
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smp_send_ipi(cpu);
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sysop("sev");
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}
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bool smp_is_alive(int cpu)
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{
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if (cpu >= MAX_CPUS)
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return false;
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return spin_table[cpu].flag;
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}
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uint64_t smp_get_mpidr(int cpu)
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{
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if (cpu >= MAX_CPUS)
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return 0;
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return spin_table[cpu].mpidr;
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}
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u64 smp_get_release_addr(int cpu)
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{
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struct spin_table *target = &spin_table[cpu];
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if (cpu >= MAX_CPUS)
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return 0;
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target->args[0] = 0;
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target->args[1] = 0;
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target->args[2] = 0;
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target->args[3] = 0;
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return (u64)&target->target;
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}
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