import sys, pathlib sys.path.append(str(pathlib.Path(__file__).resolve().parents[1])) from m1n1.setup import * from m1n1 import asm from m1n1.shell import run_shell from m1n1.gpiola import GPIOLogicAnalyzer from m1n1.hw.spi import * p.smp_start_secondaries() p.set32(0x28e580208, 1<<31) p.clear32(0x28e580208, 1<<31) spi = u.adt["arm-io/spi3"].get_reg(0)[0] regs = SPIRegs(u, spi) mon.add(spi, 0x10) mon.add(spi + 0x30, 0x10) mon.add(spi + 0x40, 0x400) aic = u.adt["arm-io/aic"].get_reg(0)[0] mon.add(aic + 0x6800 + (1109 // 32) * 4, 4) gpio = u.adt["arm-io/gpio0"].get_reg(0)[0] mon.add(gpio, 0x1c8) mon.add(gpio+0x1e0, 0x300) mon.poll() m = GPIOLogicAnalyzer(u, "arm-io/gpio0", pins={"miso": 0x34, "mosi": 0x35, "clk": 0x36, "cs": 0x37}, #pins={"miso": 0xa, "mosi": 0xb, "clk": 0x20, "cs": 0x21}, #pins={"clk": 46, "mosi": 47, "miso": 48, "cs": 49}, div=1, on_pin_change=False) #p.write32(spi + 0x100, 0xffffffff) regs.CTRL.val = 0xc regs.PIN.val = 0x2 regs.CONFIG.val = 0x20 | (1<<15) | 6 regs.CONFIG.val = 0x20 | (1<<15) | 4 regs.CONFIG.val = 0x20 | (1<<15) | 2 regs.CONFIG.val = 0x20 | (3<<15) | 0 def try_all_bits(): for i in range(0, 0x200, 4): v = p.read32(spi + i) for j in range(32): p.write32(spi + i, v ^ (1< 0x100: break time.sleep(0.001) print(f"{regs.RXCNT.val:#x} {regs.FIFO_STAT.reg} {regs.STATUS.val:#x} {regs.ISTATUS2.val:#x}") regs.STATUS.val = 0xffffffff regs.ISTATUS1.val = 0xffffffff regs.ISTATUS2.val = 0xffffffff mon.poll() while regs.FIFO_STAT.reg.LEVEL_RX: print("RX", hex(regs.RXDATA.val)) regs.CTRL.val = 0 m.complete() m.show() def poll(count=1000): lval = None for i in range(count): pins = 0x35, 0x36, 0x37 vals = [p.read32(gpio + 4 * pin) & 1 for pin in pins] if vals != lval: print(f"{i:6d}: {vals}") lval = vals mon.poll() #run_shell(globals(), msg="Have fun!")