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Author SHA1 Message Date
Hector Martin
36e0283a87 hv: Handle PAC mask automatically 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 23:28:31 +09:00
Hector Martin
5eed8f674d hv_vm: Fix guest SError handling 
This was broken, but somewhat masked by another bug in hv_vm.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 22:17:52 +09:00
Hector Martin
56c3d93787 hv_exc: Enable SErrors in the hypervisor 
This finally works properly now

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 21:18:13 +09:00
Hector Martin
78cf104b1f hv_vm: Guard emulated read/writes to catch SErrors/aborts 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 21:18:13 +09:00
Hector Martin
4f92a77efd exception: Allow guarding SError exceptions 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 21:18:13 +09:00
Hector Martin
25bc815821 hv: Store exception info regs on entry, and use it 
This is the second part of allowing nested exceptions

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 21:18:13 +09:00
Hector Martin
607464f8b0 proxy/uartproxy/hv_asm: Add syncs to flush SErrors 
This makes sure any pending memory ops that might trigger an
asynchronous SError do so here, and not later. This fixes SErrors
breaking proxy ops.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 20:31:52 +09:00
Hector Martin
d44d0a4f16 Revert "hv_asm: Unmask SErrors inside the HV" 
This reverts commit bb7c8ad3c5.

This is broken.
 2021-09-21 20:30:07 +09:00
Hector Martin
bce239b36f exception: Make space in the stack for full exception context 
This is step 1 of the rework to make reentrant exceptions work

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 20:29:19 +09:00
Hector Martin
04668b370a m1n1.proxyutils: Print and clear L2C regs on SErrors 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 17:15:49 +09:00
Hector Martin
e08457aaa9 Makefile, m1n1.ld: Build with debug info 
This allows addr2line to work. The Mach-O output should be unchanged.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 17:13:03 +09:00
Hector Martin
a16731e8b3 hv_exc: Avoid delivering spurious HV-triggered IPIs to the guest 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 17:13:03 +09:00
Hector Martin
098d394a5c exception: Handle Fast IPIs 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 13:33:23 +09:00
Hector Martin
0e3770ca47 hv, m1n1.hv: Add cpu() command to switch CPU contexts 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 13:18:06 +09:00
Hector Martin
977cbdf4f8 hv_exc: New time accounting around Python callbacks 
This does an explicit hypervisor rendezvous. It's not great because it
introduces spurious guest IPIs, but xnu doesn't seem to care...

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 13:17:00 +09:00
Hector Martin
5feae51f25 tools/run_guest.py: Add --debug-xnu argument 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 13:15:24 +09:00
Hector Martin
9545371c87 m1n1.hv: Add more PMGR hacks for xnu bug workarounds etc 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 13:15:04 +09:00
Hector Martin
64dab94821 hv_aic: Use aic.h instead of just declaring aic_base 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 00:42:19 +09:00
Hector Martin
160ced7449 m1n1.hv: Also guard IMX pstate 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 00:40:31 +09:00
Hector Martin
945b75a0f8 hv_aic: Fix regression introduced by 4b4ae3ab 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 00:40:04 +09:00
Hector Martin
16314a6203 m1n1.fw.pmp: New module 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-20 18:01:21 +09:00
Hector Martin
6211e9f9e6 m1n1.hw.pmgr: New module 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-20 18:01:09 +09:00
Hector Martin
eae9eceff1 m1n1.adt: Fix more pmgr fields, improve dump_pmgr.py 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-20 17:55:45 +09:00
Hector Martin
d2d5952aa5 tools: dump_pmgr.py 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-20 03:00:40 +09:00
Hector Martin
1e98c320df m1n1.adt: Pretty sure the v_ things were wrong 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-20 02:49:58 +09:00
Hector Martin
5c99406790 m1n1.hv: Guard UART0 pmgr regs 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-20 02:48:23 +09:00
Hector Martin
c461b5d033 m1n1.adt: Add clock-frequencies decoding 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-19 22:33:38 +09:00
Hector Martin
ffacef41ee iodev, exception: Remove gratuitous UART usage 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-19 22:33:20 +09:00
Hector Martin
6c070fa224 m1n1.proxyutils: Only set baud if connected via serial 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-19 22:32:58 +09:00
Hector Martin
99e38d24d0 experiments/cpu_pstates.py: Remove p-core boost testing hack 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-19 02:28:49 +09:00
Hector Martin
edb32c48a2 smp: Allow switching back to wfe for the smp spinloop 
This is what Linux expects, so we'd better do it in kboot.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-19 02:17:04 +09:00
Hector Martin
c8eb9a7862 experiments: Add cpu_pstate_latencies.py 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-19 02:03:27 +09:00
Hector Martin
6a620ddab9 experiments: Add cpu_pstates.py 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-19 02:03:24 +09:00
Hector Martin
c3ba77ce16 hv_exc: Handle SYS_IMP_APL_CYC_OVRD in the fast path 
m1n1 now uses this for SMP, and due to wfi FIQ leakage from the HV
timer this gets spammed thousands of times per second. Handle it in
the HV directly.

Fixes: #107

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-18 22:33:28 +09:00
Hector Martin
37b2fdda7c m1n1.adt: Handle empty function props 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-18 22:27:13 +09:00
Hector Martin
2d952752db proxy: Add smp_wait() to the proxy 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-17 15:25:34 +09:00
Hector Martin
b16bad61b4 m1n1.utils: Fix RegAccessor assignment 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-17 00:34:56 +09:00
Hector Martin
bbf8889d87 m1n1.trace.asc: Print more registers 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-17 00:34:42 +09:00
Hector Martin
36a7f3f2e1 m1n1.hw.asc: Print raw messages in hex 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-17 00:34:22 +09:00
Hector Martin
0d13ed692e m1n1.fw.asc: Align buffer sizes in reply messages 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-17 00:33:34 +09:00
Hector Martin
966b50a753 m1n1.fw.asc: Support booting an ASC 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-17 00:33:12 +09:00
Hector Martin
b53b627cb9 m1n1.hw.dart: Support initializing a DART from scratch 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-17 00:30:41 +09:00
Hector Martin
97ed24a908 m1n1.fw.asc: Make DVA offset configurable 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-17 00:30:14 +09:00
Hector Martin
b1bc4023dc smp: Use wfi and put idle CPUs in deep sleep 
This allows a single active P-Core to boost to 3.2GHz.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-17 00:15:52 +09:00
Hector Martin
77fbb05623 m1n1.adt: Pretty-print functions 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-16 17:06:51 +09:00
Hector Martin
961f8eae4d m1n1.adt: Print a useful diag when a prop fails to parse 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-16 16:48:22 +09:00
Hector Martin
de8b490b01 m1n1.adt: Add some mcc props 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-16 16:47:45 +09:00
Hector Martin
3b6a645db6 m1n1.adt: Support master (templated) ADTs properly 
They used to parse but not round-trip, now they do

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-16 16:47:22 +09:00
Hector Martin
10880ca1a6 hv_vm: Unbork >32bit mmiotrace 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-16 03:01:10 +09:00
Hector Martin
9ecaeb9e1b m1n1.hv: Add SMP support 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-15 23:32:57 +09:00