This unborks reloading, since otherwise non-reloaded modules can clobber
symbols from reloaded modules with their old versions
Signed-off-by: Asahi Lina <lina@asahilina.net>
Handy for ringbuf pointer type structures where we need to be able to
read/write individual members using atomic primitives, without going
through Construct.
Signed-off-by: Asahi Lina <lina@asahilina.net>
This allows alternative BaseRegMap subclasses to dynamically build the
map instead of doing the metaclass stuff.
Signed-off-by: Asahi Lina <lina@asahilina.net>
This stops DCP from killing our modeset if the connection cycles.
Also force a (potential) configure cycle if the display is external;
this makes sure updated stage2s will have a chance at fixing issues of
old stage1s. Modesetting is fast when it's the same mode as before.
Signed-off-by: Hector Martin <marcan@marcan.st>
Get rid of asc_cpu_stop() which was never a thing. The CPU start bit
should always be off in the steady state, it is only used momentarily to
start the CPU.
Signed-off-by: Hector Martin <marcan@marcan.st>
Technically both can be done unconditionally, but let's be explicit in
the python side to see if we ever find this algorithm doesn't work.
Signed-off-by: Hector Martin <marcan@marcan.st>
Add script which prints out the (rough) measured impedance of connected
headphones on machines with the CS42L84 jack codec (2021 Macbook Pros).
$ proxyclient/experiments/ohmmeter.py
Waiting for plug... measuring... 64.3 ohms... yanked
Waiting for plug... measuring... 697.1 ohms...
Signed-off-by: Martin Povišer <povik@protonmail.com>
Fix reading of registers (there have been STOPs issued between the two
messages which surprisingly went unnoticed until now). Also add support
for multibyte register addresses.
Signed-off-by: Martin Povišer <povik@protonmail.com>
Commit 9c795fbdbf introduced the pair of
WFE and SEV for spinlock, but it caused delays of tens of seconds. A
possible explanation for the delay is lack of data synchronization
barrier between the store instruction and SEV instruction.
Arm Architecture Reference Manual for A-profile architecture (issue H.a)
says:
> Arm recommends that software includes a Data Synchronization Barrier
> (DSB) instruction before any SEV instruction. The DSB instruction
> ensures that no instructions, including any SEV instructions, that
> appear in program order after the DSB instruction, can execute until
> the DSB instruction has completed.
However, inserting a DSB instruction still didn't resolve the delay.
The exclusive load is an alternative to the SEV instruction. The manual
says:
> ...However, in Armv8, when the global monitor for a PE changes from
> Exclusive Access state to Open Access state, an event is generated.
> This is equivalent to issuing an SEVL instruction on the PE for which
> the monitor state has changed. It removes the need for spinlock code
> to include an SEV instruction after clearing a spinlock.
As an additional benefit, the exclusive load is local to the PE and
eliminates spurious events for other PEs.
Trusted Firmware-A v2.6 also employs the same algorithm.
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
