Previously RAM was mapped ad-hoc, but this can end up interacting
poorly with the tracer infrastructure which we are now using for RAM
too. Move to mapping guest RAM via the tracer infra, and also unmap the
TZ carveouts in the Python side so it knows about them.
This is a HV ABI break.
Signed-off-by: Asahi Lina <lina@asahilina.net>
This turns on the system level cache. The carveout unmapping also moves
here, and now it handles T8103/T6000 properly.
Signed-off-by: Hector Martin <marcan@marcan.st>
