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245 commits 13 branches 49 tags 8.6 MiB
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96 commits

Author SHA1 Message Date
Hector Martin
1ae60ad715 hv: Beginnings of a hypervisor 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-01 19:21:33 +09:00
Hector Martin
4547773edf setup.py: Remove unnecessary imports 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-01 19:04:01 +09:00
Hector Martin
63366e43d2 proxy.py: Fix typo 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-01 19:03:46 +09:00
Hector Martin
5fdeb1c3e3 chainload.py: Remove useless import 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-01 19:03:21 +09:00
Hector Martin
8b1ea3f04d proxyutils: Make heap size configurable 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-01 19:02:25 +09:00
Hector Martin
2a1a04ea0d setup.py: Move baudrate auto setup to proxyutils 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-01 19:02:20 +09:00
Hector Martin
7c2dace0b0 chainload.py: Cleanup, move Mach-O loader to macho.py 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-01 15:16:02 +09:00
Hector Martin
a489a646bd Add tools for ARM sysreg database management 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-01 15:14:35 +09:00
Hector Martin
7bb490eb58 utils.py: New file for misc util functions (non proxy) 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-01 15:13:29 +09:00
Hector Martin
aaf4b2785b Rename utils.py -> proxyutils.py 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-01 15:13:06 +09:00
Hector Martin
fcd103b2a4 proxy.py: Reopen port on reboot if necessary 
This is needed for USB mode, as the device re-enumerates after a reboot.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-04-27 19:49:59 +09:00
Hector Martin
80f73926e8 proxy.py: Move M1N1DEVICE/UART port open logic into UartInterface 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-04-27 19:49:59 +09:00
Jean-Francois Bortolotti
82978081f8 chainload.py: Fix el1 support 
Signed-off-by: Jean-Francois Bortolotti <jeff@borto.fr>
 2021-04-18 02:29:32 +09:00
Hector Martin
f6297437c0 linux.py: Allow specifying a separate TTY device 
This allows e.g. opening a TTY on the UART serial device after
booting the kernel via USB.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-04-17 18:12:59 +09:00
Hector Martin
7dfe24ee2c Rework kboot/chainload flow to shut down before calling the next stage 
Next stage boots now exit back to main() after replying to the proxy
command, allowing shutdown functions to be called. Introduces a new
P_VECTOR proxy op, distinct from P_CALL. The Python side is reworked
to remain compatible with older versions that do not support this.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-04-17 18:12:59 +09:00
Hector Martin
88e1612c09 uartproxy: s/CRCERR/CSUMERR/ and actually use it 
It's not a CRC.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-04-17 16:25:48 +09:00
Hector Martin
8104ec02c4 iodev: Add proxy ops 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-04-15 23:18:57 +09:00
Hector Martin
ce79483165 proxy: Add support for passing buffer/string values to reqs 
This only works if the utils class has been instantiated, which is a bit
of a hack.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-04-15 23:18:57 +09:00
Hector Martin
f8c1c65cf9 Revert "proxy: add fb console console ops" 
This reverts commit de0456b9a5.

These ops become redundant with the new iodev control op.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-04-15 23:18:57 +09:00
Sven Peter
35007b700e proxy: add dart ops 
Signed-off-by: Sven Peter <sven@svenpeter.dev>
 2021-04-15 01:36:29 +09:00
Hector Martin
6d87b3b016 chainload.py: Improve chainloading 
- Support chainload-in-place
- Do Mach-O loading host-side
- Handle copying SEPFW (WIP, ADT not updated yet)

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-04-14 21:13:19 +09:00
Hector Martin
b40fffea20 adt.py: Add basic ADT parser 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-04-14 21:12:38 +09:00
Sven Peter
de0456b9a5 proxy: add fb console console ops 
Signed-off-by: Sven Peter <sven@svenpeter.dev>
 2021-04-14 18:11:37 +09:00
Hector Martin
0df6db324b timer_test.py: More exhaustive tests 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-04-14 17:48:02 +09:00
Hector Martin
f30e91b933 asm.py: Build for ARMv8.2-A 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-04-14 17:48:01 +09:00
Sven Peter
1314a426e2 proxyclient: add PMGR ops 
Signed-off-by: Sven Peter <sven@svenpeter.dev>
 2021-04-11 05:26:29 +09:00
Sven Peter
f17a15d19a proxyclient/i2c: experiment with the i2c and ti usb chip 
Signed-off-by: Sven Peter <sven@svenpeter.dev>
 2021-04-09 14:47:22 +09:00
Sven Peter
8aa3c69a2d tunables: add tunables_apply_local_addr 
Signed-off-by: Sven Peter <sven@svenpeter.dev>
 2021-04-08 20:32:12 +09:00
Sven Peter
a17e64f1e2 tunables: add proxy ops 
Signed-off-by: Sven Peter <sven@svenpeter.dev>
 2021-04-08 20:32:12 +09:00
Sven Peter
ed72fe443c proxyclient/asm.py: allow to override compiler prefix 
Signed-off-by: Sven Peter <sven@svenpeter.dev>
 2021-04-05 23:49:25 +09:00
Hector Martin
3a42f80a73 chainload.py: Set up sane EL1 config for timers/IRQs 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-03-28 19:31:14 +09:00
Hector Martin
70f6bc7514 linux.py: support up to 512MB kernels 
Some people apparently have the patience to load KASAN kernels over
serial :-)

Also bump the python-managed heap to 1GB.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-03-08 01:33:43 +09:00
Hector Martin
3c514e826c fptest.py: test Apple floating-point controls 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-03-04 23:22:41 +09:00
Hector Martin
db49cc92f3 hacr_trap_bits.py: figure out HACR_EL2 sysreg traps 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-03-04 23:20:50 +09:00
Hector Martin
1a880518b0 chainload.py: implement chainloading at EL1 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-03-04 22:41:06 +09:00
Hector Martin
3bf3613e7d find_all_regs: print EL2-only registers 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-03-04 22:40:25 +09:00
Hector Martin
b8349819fe Implement calling code as EL1 
This works by clearing HCR_EL2.TGE, and then doing essentially the same
thunk/return dance as for EL0 calls. However, since most EL1 exceptions
are not routed to EL2, we install hypercall vectors in EL1 to forward
them to EL2, and then short circuit the exception return to whatever
triggered the original exception.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-03-04 22:10:37 +09:00
Hector Martin
acf1198fbb timer_test.py: add test of HV/guest timers 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-03-01 01:47:42 +09:00
Hector Martin
0f2be2c0ee utils.py: unbork inst() 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-03-01 01:45:39 +09:00
Hector Martin
2f959f758c find_all_regs.py: show EL0-accessible registers 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-02-25 00:33:00 +09:00
Hector Martin
d918b066b6 utils.py: add silent and call arguments to msr/mrs 
call allows the caller to override the function used for the function
call, e.g. to use EL0.

Use silent=True for find_all_regs.py

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-02-25 00:30:58 +09:00
Hector Martin
3872b1a7da exception: implement el0_call to run code as EL0 
This lets us test register access and other features from EL0.

No serious attempt at security is made, but at least EL0 runs off of a
separate stack and can return to EL2 at any time with `brk`; we can
easily implement a guard mode to break straight to EL2 on exception
later if needed.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-02-24 21:48:12 +09:00
Hector Martin
73a85be2b8 memory: prepare for EL0 support 
Enable EL0 access to MMIO/etc, but not main RAM, because AArch64
architecturally enforces EL0w ^ EL2x.

Instead, create an alias of main RAM to grant EL0 full permissions,
at 0x80_0000_0000.

Grant EL0 full access to MMIO stuff, since EL2 will never execute
from there.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-02-24 21:48:12 +09:00
Hector Martin
a0960fca81 find_all_regs.py: test writability 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-02-24 21:48:12 +09:00
Hector Martin
65824016b7 utils.py add silent argument to inst() 2021-02-24 19:01:17 +09:00
Hector Martin
64306e78a0 linux.py: only mask DAIF.IF 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-02-21 11:55:54 +09:00
Sven Peter
54a147013f chainload.py: compress payload to improve loading time 
Signed-off-by: Sven Peter <sven@svenpeter.dev>
 2021-02-20 01:29:46 +09:00
Sven Peter
fa02cc9602 utils.py: add compressed writemem 
Signed-off-by: Sven Peter <sven@svenpeter.dev>
 2021-02-20 01:29:46 +09:00
Hector Martin
b7d30250b2 utils: allow inst() to return r0 and take args 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-02-19 03:25:28 +09:00
Sven Peter
870fead39c proxyclient: add ops for writeread{8,16,32,64} 
Signed-off-by: Sven Peter <sven@svenpeter.dev>
 2021-02-18 16:12:28 +09:00