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https://github.com/AsahiLinux/m1n1
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m1n1.hw.uat: Implement iomap
Signed-off-by: Scott Mansell <phiren@gmail.com>
This commit is contained in:
Scott Mansell
Asahi Lina
parent
43e3e0f3c2
commit
fe9c1f4bca
1 changed files with 102 additions and 78 deletions
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@ -10,9 +10,10 @@
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import struct
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from ..utils import *
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from enum import Enum
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from ..malloc import Heap
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from enum import IntEnum
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class MemoryAttr(Enum):
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class MemoryAttr(IntEnum):
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Normal = 0 # Only accessed by the gfx-asc coprocessor
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Device = 1
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Shared = 2 # Probally Outer-shareable. Shared with either the main cpu or AGX hardware
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@ -29,11 +30,15 @@ class TTBR(Register64):
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def offset(self):
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return self.BADDR << 1
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def set_offset(self, offset):
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self.BADDR = offset >> 1
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def describe(self):
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return f"{self.offset():x} [ASID={self.ASID}, CnP={self.CnP}]"
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class PTE(Register64):
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OFFSET = 47, 14
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UNK0 = 10 # probally an ownership flag, seems to be 1 for FW created PTEs and 0 for OS PTEs
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TYPE = 1
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VALID = 0
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@ -43,24 +48,26 @@ class PTE(Register64):
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def offset(self):
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return self.OFFSET << 14
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def set_offset(self, offset):
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self.OFFSET = offset >> 14
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def describe(self):
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if not self.valid():
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return f"<invalid> [{int(self)}:x]"
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return f"{self.offset():x}"
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return f"{self.offset():x}, UNK={self.UNK0}"
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class Page_PTE(Register64):
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OS = 55 # Owned by host os or firmware
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UXN = 54
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PXN = 53
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OFFSET = 47, 14
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nG = 11 # global or local TLB caching
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AF = 10
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SH = 9, 8
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AP = 7, 6
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AP_el0 = 6
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OS = 55 # Owned by host os or firmware
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UXN = 54
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PXN = 53
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OFFSET = 47, 14
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nG = 11 # global or local TLB caching
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AF = 10
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SH = 9, 8
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AP = 7, 6
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AttrIndex = 4, 2
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TYPE = 1
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VALID = 0
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TYPE = 1
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VALID = 0
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def valid(self):
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return self.VALID == 1 and self.TYPE == 1
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@ -68,6 +75,9 @@ class Page_PTE(Register64):
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def offset(self):
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return self.OFFSET << 14
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def set_offset(self, offset):
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self.OFFSET = offset >> 14
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def access(self, el):
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if el == 0:
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return [["Xo", "RW", "Xo", "RX"],
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@ -170,13 +180,13 @@ class UAT(Reloadable):
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(L3_OFF, Lx_SIZE, Page_PTE),
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]
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def __init__(self, iface, util=None, hv=None, iova_range=(0x80000000, 0x90000000)):
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def __init__(self, iface, util=None, hv=None):
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self.iface = iface
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self.u = util
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self.hv = hv
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self.pt_cache = {}
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#self.iova_allocator = [Heap(iova_range[0], iova_range[1], self.PAGE_SIZE)
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# for i in range(16)]
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self.dirty = set()
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self.ctx_allocator = {}
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self.ttbr = None
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self.VA_MASK = 0
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@ -184,9 +194,28 @@ class UAT(Reloadable):
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self.VA_MASK |= (size - 1) << off
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self.VA_MASK |= self.PAGE_SIZE - 1
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# Implements the OS side of UAT initilzion
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def initilize(self, ttbr, ttbr1_addr, kernel_va_base):
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self.ttbr = ttbr
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# create the ttbr1 allocator at ctx 0
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self.get_allocator(0, (kernel_va_base, kernel_va_base + 0x1_00000000))
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# set ttbr0 and ttbr1, which are needed for gfx_asc to start
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ttbr0_addr = self.u.memalign(self.PAGE_SIZE, self.PAGE_SIZE)
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self.write_pte(ttbr, 0, 2, TTBR(BADDR = ttbr0_addr >> 1, ASID = 0))
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self.write_pte(ttbr, 1, 2, TTBR(BADDR = ttbr1_addr >> 1, ASID = 0))
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self.flush_dirty()
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def set_ttbr(self, addr):
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self.ttbr = addr
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def get_allocator(self, ctx, range=(0x16_00000000, 0x17_00000000)):
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if ctx not in self.ctx_allocator:
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self.ctx_allocator[ctx] = Heap(range[0], range[1], self.PAGE_SIZE)
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return self.ctx_allocator[ctx]
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def ioread(self, ctx, base, size):
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if size == 0:
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return b""
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@ -218,86 +247,74 @@ class UAT(Reloadable):
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p += size
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iova += size
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# A stream interface that can be used for random access by Construct
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def iostream(self, ctx, base):
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return UatStream(self, ctx, base)
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# TODO: fix this
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# def iomap(self, stream, addr, size):
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# iova = self.iova_allocator[stream].malloc(size)
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def iomap(self, ctx, addr, size, flags= None):
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iova = self.get_allocator(ctx).malloc(size)
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# self.iomap_at(stream, iova, addr, size)
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# return iova
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self.iomap_at(ctx, iova, addr, size, flags)
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return iova
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# def iomap_at(self, stream, iova, addr, size):
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# if size == 0:
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# return
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def iomap_at(self, ctx, iova, addr, size, flags= None):
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if size == 0:
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return
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# if not (self.enabled_streams & (1 << stream)):
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# self.enabled_streams |= (1 << stream)
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# self.regs.ENABLED_STREAMS.val |= self.enabled_streams
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if addr & (self.PAGE_SIZE - 1):
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raise Exception(f"Unaligned PA {addr:#x}")
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# tcr = self.regs.TCR[stream].reg
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if iova & (self.PAGE_SIZE - 1):
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raise Exception(f"Unaligned IOVA {iova:#x}")
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# if addr & (self.PAGE_SIZE - 1):
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# raise Exception(f"Unaligned PA {addr:#x}")
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if flags == None:
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flags = {'OS': 1, 'AttrIndex': MemoryAttr.Normal, 'VALID': 1, 'TYPE': 1, 'AP': 1, 'AF': 1, 'UXN': 1}
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# if iova & (self.PAGE_SIZE - 1):
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# raise Exception(f"Unaligned IOVA {iova:#x}")
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start_page = align_down(iova, self.PAGE_SIZE)
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end = iova + size
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end_page = align_up(end, self.PAGE_SIZE)
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# start_page = align_down(iova, self.PAGE_SIZE)
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# end = iova + size
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# end_page = align_up(end, self.PAGE_SIZE)
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for page in range(start_page, end_page, self.PAGE_SIZE):
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table_addr = self.ttbr + ctx * 16
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for (offset, size, ptecls) in self.LEVELS:
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if ptecls is Page_PTE:
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pte = Page_PTE(**flags)
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pte.set_offset(addr)
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self.write_pte(table_addr, page >> offset, size, pte)
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addr += self.PAGE_SIZE
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else:
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pte = self.fetch_pte(table_addr, page >> offset, size, ptecls)
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if not pte.valid():
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pte.set_offset(self.u.memalign(self.PAGE_SIZE, self.PAGE_SIZE))
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if ptecls is not TTBR:
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pte.VALID = 1
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pte.TYPE = 1
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#pte.UNK0 = 1
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self.write_pte(table_addr, page >> offset, size, pte)
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table_addr = pte.offset()
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# dirty = set()
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self.flush_dirty()
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# for page in range(start_page, end_page, self.PAGE_SIZE):
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# paddr = addr + page - start_page
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# l0 = page >> self.L0_OFF
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# assert l0 < self.L0_SIZE
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# ttbr = self.regs.TTBR[stream, l0].reg
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# if not ttbr.VALID:
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# l1addr = self.u.memalign(self.PAGE_SIZE, self.PAGE_SIZE)
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# self.pt_cache[l1addr] = [0] * self.Lx_SIZE
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# ttbr.VALID = 1
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# ttbr.ADDR = l1addr >> 12
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# self.regs.TTBR[stream, l0].reg = ttbr
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# cached, l1 = self.get_pt(ttbr.ADDR << 12)
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# l1idx = (page >> self.L1_OFF) & self.IDX_MASK
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# l1pte = self.ptecls(l1[l1idx])
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# if not l1pte.VALID:
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# l2addr = self.u.memalign(self.PAGE_SIZE, self.PAGE_SIZE)
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# self.pt_cache[l2addr] = [0] * self.Lx_SIZE
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# l1pte = self.ptecls(
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# OFFSET=l2addr >> self.PAGE_BITS, VALID=1, SP_PROT_DIS=1)
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# l1[l1idx] = l1pte.value
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# dirty.add(ttbr.ADDR << 12)
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# else:
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# l2addr = l1pte.OFFSET << self.PAGE_BITS
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# dirty.add(l1pte.OFFSET << self.PAGE_BITS)
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# cached, l2 = self.get_pt(l2addr)
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# l2idx = (page >> self.L2_OFF) & self.IDX_MASK
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# self.pt_cache[l2addr][l2idx] = self.ptecls(
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# SP_START=0, SP_END=0xfff,
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# OFFSET=paddr >> self.PAGE_BITS, VALID=1, SP_PROT_DIS=1).value
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# for page in dirty:
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# self.flush_pt(page)
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def fetch_pte(self, offset, idx, size, ptecls):
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idx = idx & (size - 1)
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cached, level = self.get_pt(offset, size=size)
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pte = ptecls(level[idx])
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cached, table = self.get_pt(offset, size=size)
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pte = ptecls(table[idx])
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if not pte.valid() and cached:
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cached, level = self.get_pt(offset, size=size, uncached=True)
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pte = ptecls(level[idx])
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#print(f"fetch_pte {size} {offset:#x} {idx:#x} {int(pte):#x}")
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cached, table = self.get_pt(offset, size=size, uncached=True)
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pte = ptecls(table[idx])
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return pte
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def write_pte(self, offset, idx, size, pte):
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idx = idx & (size - 1)
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cached, table = self.get_pt(offset, size=size)
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table[idx] = pte.value
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self.dirty.add(offset)
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def iotranslate(self, ctx, start, size):
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if size == 0:
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@ -360,7 +377,14 @@ class UAT(Reloadable):
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def flush_pt(self, addr):
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assert addr in self.pt_cache
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self.iface.writemem(addr, struct.pack(f"<{self.Lx_SIZE}Q", *self.pt_cache[addr]))
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table = self.pt_cache[addr]
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self.iface.writemem(addr, struct.pack(f"<{len(table)}Q", *table))
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def flush_dirty(self):
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for page in self.dirty:
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self.flush_pt(page)
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self.dirty.clear()
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def invalidate_cache(self):
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self.pt_cache = {}
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