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cpu_regs: Add more chicken bit names

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These are from a public Apple source that shall remain unidentified
(because it's utterly silly that they keep trying to hide these).

Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin 2022-07-17 03:17:13 +09:00
parent ee0667e190
commit f61e5d4958
4 changed files with 66 additions and 52 deletions
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30
src/chickens_avalanche.c
View file

@ -5,8 +5,10 @@
static void init_common_avalanche(void)
{
reg_mask(SYS_IMP_APL_HID1, HID1_AVL_UNK42_MASK, HID1_AVL_UNK42(1));
reg_mask(SYS_IMP_APL_HID1, HID1_AVL_UNK22_MASK, HID1_AVL_UNK22(3));
reg_mask(SYS_IMP_APL_HID1, HID1_ZCL_RF_MISPREDICT_THRESHOLD_MASK,
HID1_ZCL_RF_MISPREDICT_THRESHOLD(1));
reg_mask(SYS_IMP_APL_HID1, HID1_ZCL_RF_RESTART_THRESHOLD_MASK,
HID1_ZCL_RF_RESTART_THRESHOLD(3));
reg_set(SYS_IMP_APL_HID11, HID11_DISABLE_LD_NT_WIDGET);
@ -15,24 +17,26 @@ static void init_common_avalanche(void)
// "configure dummy cycles to work around incorrect temp sensor readings on
// NEX power gating" (maybe)
reg_mask(SYS_IMP_APL_HID13,
HID13_AVL_UNK0_MASK | HID13_AVL_UNK7_MASK | HID13_PRE_CYCLES_MASK |
HID13_AVL_UNK26_MASK | HID13_AVL_UNK30_MASK | HID13_AVL_UNK34_MASK |
HID13_AVL_UNK38_MASK | HID13_AVL_UNK42_MASK | HID13_AVL_UNK46_MASK |
HID13_AVL_UNK50_MASK | HID13_RESET_CYCLE_COUNT_MASK,
HID13_AVL_UNK0(8) | HID13_AVL_UNK7(8) | HID13_PRE_CYCLES(1) | HID13_AVL_UNK26(4) |
HID13_AVL_UNK30(4) | HID13_AVL_UNK34(4) | HID13_AVL_UNK38(4) | HID13_AVL_UNK42(4) |
HID13_AVL_UNK46(4) | HID13_AVL_UNK50(4) | HID13_RESET_CYCLE_COUNT(0));
HID13_POST_OFF_CYCLES_MASK | HID13_POST_ON_CYCLES_MASK | HID13_PRE_CYCLES_MASK |
HID13_GROUP0_FF1_DELAY_MASK | HID13_GROUP0_FF2_DELAY_MASK |
HID13_GROUP0_FF3_DELAY_MASK | HID13_GROUP0_FF4_DELAY_MASK |
HID13_GROUP0_FF5_DELAY_MASK | HID13_GROUP0_FF6_DELAY_MASK |
HID13_GROUP0_FF7_DELAY_MASK | HID13_RESET_CYCLES_MASK,
HID13_POST_OFF_CYCLES(8) | HID13_POST_ON_CYCLES(8) | HID13_PRE_CYCLES(1) |
HID13_GROUP0_FF1_DELAY(4) | HID13_GROUP0_FF2_DELAY(4) | HID13_GROUP0_FF3_DELAY(4) |
HID13_GROUP0_FF4_DELAY(4) | HID13_GROUP0_FF5_DELAY(4) | HID13_GROUP0_FF6_DELAY(4) |
HID13_GROUP0_FF7_DELAY(4) | HID13_RESET_CYCLES(0));
// No idea what the correct name for these registers is
reg_mask(s3_0_c15_c0_3, GENMASK(7, 0) | GENMASK(43, 36), (0x1aULL << 0) | (0x1fULL << 36));
reg_mask(s3_0_c15_c0_4, GENMASK(15, 8), (0x1fULL << 8));
reg_mask(SYS_IMP_APL_HID26, HID26_GROUP1_OFFSET_MASK | HID26_GROUP2_OFFSET_MASK,
HID26_GROUP1_OFFSET(26) | HID26_GROUP2_OFFSET(31));
reg_mask(SYS_IMP_APL_HID27, HID27_GROUP3_OFFSET_MASK, HID27_GROUP3_OFFSET(31));
}
static void init_m2_avalanche(void)
{
init_common_avalanche();
reg_mask(SYS_IMP_APL_HID3, HID3_AVL_UNK57_MASK, HID3_AVL_UNK57(0x3c));
reg_mask(SYS_IMP_APL_HID3, HID3_DEV_PCIE_THROTTLE_LIMIT_MASK, HID3_DEV_PCIE_THROTTLE_LIMIT(60));
reg_set(SYS_IMP_APL_HID3, HID3_DEV_PCIE_THROTTLE_ENABLE);
reg_set(SYS_IMP_APL_HID18, HID18_AVL_UNK27 | HID18_AVL_UNK29);
reg_set(SYS_IMP_APL_HID16, HID16_AVL_UNK12);

4
src/chickens_blizzard.c
View file

@ -12,7 +12,7 @@ void init_m2_blizzard(void)
{
init_common_blizzard();
reg_mask(SYS_IMP_APL_EHID9, EHID9_BLZ_UNK6_MASK, EHID9_BLZ_UNK6(0x3c));
reg_set(SYS_IMP_APL_EHID9, EHID9_DEV_THROTTLE_2_ENABLE);
reg_mask(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_LIMIT_MASK, EHID9_DEV_2_THROTTLE_LIMIT(60));
reg_set(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_ENABLE);
reg_set(SYS_IMP_APL_EHID18, EHID18_BLZ_UNK34);
}

2
src/chickens_icestorm.c
View file

@ -8,7 +8,7 @@ static void init_common_icestorm(void)
// "Sibling Merge in LLC can cause UC load to violate ARM Memory Ordering Rules."
reg_set(SYS_IMP_APL_HID5, HID5_DISABLE_FILL_2C_MERGE);
reg_clr(SYS_IMP_APL_EHID9, EHID9_DEV_THROTTLE_2_ENABLE);
reg_clr(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_ENABLE);
// "Prevent store-to-load forwarding for UC memory to avoid barrier ordering
// violation"

82
src/cpu_regs.h
View file

@ -32,16 +32,16 @@
#define HID1_ENABLE_MDSB_STALL_PIPELINE_ECO BIT(58)
#define HID1_ENABLE_BR_KILL_LIMIT BIT(60)
#define HID1_AVL_UNK22_MASK GENMASK(23, 22)
#define HID1_AVL_UNK22(x) (((unsigned long)x) << 22)
#define HID1_AVL_UNK42_MASK GENMASK(43, 42)
#define HID1_AVL_UNK42(x) (((unsigned long)x) << 42)
#define HID1_ZCL_RF_RESTART_THRESHOLD_MASK GENMASK(23, 22)
#define HID1_ZCL_RF_RESTART_THRESHOLD(x) (((unsigned long)x) << 22)
#define HID1_ZCL_RF_MISPREDICT_THRESHOLD_MASK GENMASK(43, 42)
#define HID1_ZCL_RF_MISPREDICT_THRESHOLD(x) (((unsigned long)x) << 42)
#define SYS_IMP_APL_HID3 sys_reg(3, 0, 15, 3, 0)
#define HID3_DISABLE_ARBITER_FIX_BIF_CRD BIT(44)
#define HID3_AVL_UNK57_MASK GENMASK(62, 57)
#define HID3_AVL_UNK57(x) (((unsigned long)x) << 57)
#define HID3_DEV_PCIE_THROTTLE_ENABLE BIT(63)
#define SYS_IMP_APL_HID3 sys_reg(3, 0, 15, 3, 0)
#define HID3_DISABLE_ARBITER_FIX_BIF_CRD BIT(44)
#define HID3_DEV_PCIE_THROTTLE_LIMIT_MASK GENMASK(62, 57)
#define HID3_DEV_PCIE_THROTTLE_LIMIT(x) (((unsigned long)x) << 57)
#define HID3_DEV_PCIE_THROTTLE_ENABLE BIT(63)
#define SYS_IMP_APL_HID4 sys_reg(3, 0, 15, 4, 0)
#define SYS_IMP_APL_EHID4 sys_reg(3, 0, 15, 4, 1)
@ -72,10 +72,10 @@
#define HID9_FIX_BUG_51667805 BIT(48)
#define HID9_FIX_BUG_55719865 BIT(55)
#define SYS_IMP_APL_EHID9 sys_reg(3, 0, 15, 9, 1)
#define EHID9_DEV_THROTTLE_2_ENABLE BIT(5)
#define EHID9_BLZ_UNK6_MASK GENMASK(11, 6)
#define EHID9_BLZ_UNK6(x) (((unsigned long)x) << 6)
#define SYS_IMP_APL_EHID9 sys_reg(3, 0, 15, 9, 1)
#define EHID9_DEV_2_THROTTLE_ENABLE BIT(5)
#define EHID9_DEV_2_THROTTLE_LIMIT_MASK GENMASK(11, 6)
#define EHID9_DEV_2_THROTTLE_LIMIT(x) (((unsigned long)x) << 6)
#define SYS_IMP_APL_HID10 sys_reg(3, 0, 15, 10, 0)
#define SYS_IMP_APL_EHID10 sys_reg(3, 0, 15, 10, 1)
@ -86,29 +86,29 @@
#define HID11_ENABLE_FIX_UC_55719865 BIT(15)
#define HID11_DISABLE_LD_NT_WIDGET BIT(59)
#define SYS_IMP_APL_HID13 sys_reg(3, 0, 15, 14, 0)
#define HID13_AVL_UNK0(x) (((unsigned long)x))
#define HID13_AVL_UNK0_MASK GENMASK(6, 0)
#define HID13_AVL_UNK7(x) (((unsigned long)x) << 7)
#define HID13_AVL_UNK7_MASK GENMASK(13, 7)
#define HID13_PRE_CYCLES(x) (((unsigned long)x) << 14)
#define HID13_PRE_CYCLES_MASK GENMASK(17, 14)
#define HID13_AVL_UNK26(x) (((unsigned long)x) << 26)
#define HID13_AVL_UNK26_MASK GENMASK(29, 26)
#define HID13_AVL_UNK30(x) (((unsigned long)x) << 30)
#define HID13_AVL_UNK30_MASK GENMASK(33, 30)
#define HID13_AVL_UNK34(x) (((unsigned long)x) << 34)
#define HID13_AVL_UNK34_MASK GENMASK(37, 34)
#define HID13_AVL_UNK38(x) (((unsigned long)x) << 38)
#define HID13_AVL_UNK38_MASK GENMASK(41, 38)
#define HID13_AVL_UNK42(x) (((unsigned long)x) << 42)
#define HID13_AVL_UNK42_MASK GENMASK(45, 42)
#define HID13_AVL_UNK46(x) (((unsigned long)x) << 46)
#define HID13_AVL_UNK46_MASK GENMASK(49, 46)
#define HID13_AVL_UNK50(x) (((unsigned long)x) << 50)
#define HID13_AVL_UNK50_MASK GENMASK(53, 50)
#define HID13_RESET_CYCLE_COUNT(x) (((unsigned long)x) << 60)
#define HID13_RESET_CYCLE_COUNT_MASK (0xFUL << 60)
#define SYS_IMP_APL_HID13 sys_reg(3, 0, 15, 14, 0)
#define HID13_POST_OFF_CYCLES(x) (((unsigned long)x))
#define HID13_POST_OFF_CYCLES_MASK GENMASK(6, 0)
#define HID13_POST_ON_CYCLES(x) (((unsigned long)x) << 7)
#define HID13_POST_ON_CYCLES_MASK GENMASK(13, 7)
#define HID13_PRE_CYCLES(x) (((unsigned long)x) << 14)
#define HID13_PRE_CYCLES_MASK GENMASK(17, 14)
#define HID13_GROUP0_FF1_DELAY(x) (((unsigned long)x) << 26)
#define HID13_GROUP0_FF1_DELAY_MASK GENMASK(29, 26)
#define HID13_GROUP0_FF2_DELAY(x) (((unsigned long)x) << 30)
#define HID13_GROUP0_FF2_DELAY_MASK GENMASK(33, 30)
#define HID13_GROUP0_FF3_DELAY(x) (((unsigned long)x) << 34)
#define HID13_GROUP0_FF3_DELAY_MASK GENMASK(37, 34)
#define HID13_GROUP0_FF4_DELAY(x) (((unsigned long)x) << 38)
#define HID13_GROUP0_FF4_DELAY_MASK GENMASK(41, 38)
#define HID13_GROUP0_FF5_DELAY(x) (((unsigned long)x) << 42)
#define HID13_GROUP0_FF5_DELAY_MASK GENMASK(45, 42)
#define HID13_GROUP0_FF6_DELAY(x) (((unsigned long)x) << 46)
#define HID13_GROUP0_FF6_DELAY_MASK GENMASK(49, 46)
#define HID13_GROUP0_FF7_DELAY(x) (((unsigned long)x) << 50)
#define HID13_GROUP0_FF7_DELAY_MASK GENMASK(53, 50)
#define HID13_RESET_CYCLES(x) (((unsigned long)x) << 60)
#define HID13_RESET_CYCLES_MASK (0xFUL << 60)
#define SYS_IMP_APL_HID16 sys_reg(3, 0, 15, 15, 2)
#define HID16_AVL_UNK12 BIT(12)
@ -140,6 +140,16 @@
#define HID21_DISABLE_CDP_REPLY_PURGED_TRANSACTION BIT(34)
#define HID21_AVL_UNK52 BIT(52)
#define SYS_IMP_APL_HID26 sys_reg(3, 0, 15, 0, 3)
#define HID26_GROUP1_OFFSET(x) (((unsigned long)x) << 0)
#define HID26_GROUP1_OFFSET_MASK (0xffUL << 0)
#define HID26_GROUP2_OFFSET(x) (((unsigned long)x) << 36)
#define HID26_GROUP2_OFFSET_MASK (0xffUL << 36)
#define SYS_IMP_APL_HID27 sys_reg(3, 0, 15, 0, 4)
#define HID27_GROUP3_OFFSET(x) (((unsigned long)x) << 8)
#define HID27_GROUP3_OFFSET_MASK (0xffUL << 8)
#define SYS_IMP_APL_PMCR0 sys_reg(3, 1, 15, 0, 0)
#define PMCR0_CNT_EN_MASK (MASK(8) | GENMASK(33, 32))
#define PMCR0_IMODE_OFF (0 << 8)