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https://github.com/AsahiLinux/m1n1
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memory.h/c: add basic MMU code
Signed-off-by: Sven Peter <sven@svenpeter.dev>
This commit is contained in:
Sven Peter
Hector Martin
parent
e08c6c98db
commit
f1c494e5ae
2 changed files with 219 additions and 0 deletions
217
src/memory.c
217
src/memory.c
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@ -3,6 +3,7 @@
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#include "memory.h"
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#include "utils.h"
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#define PAGE_SIZE 0x4000
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#define CACHE_LINE_SIZE 64
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#define CACHE_RANGE_OP(func, op) \
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@ -22,3 +23,219 @@ CACHE_RANGE_OP(dc_zva_range, "dc zva")
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CACHE_RANGE_OP(dc_cvac_range, "dc cvac")
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CACHE_RANGE_OP(dc_cvau_range, "dc cvau")
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CACHE_RANGE_OP(dc_civac_range, "dc civac")
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static inline uint64_t read_sctl(void)
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{
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sysop("isb");
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return mrs(SCTLR_EL2);
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}
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static inline void write_sctl(uint64_t val)
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{
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msr(SCTLR_EL2, val);
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sysop("isb");
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}
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/*
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* We have to use 16KB pages on the M1 which would usually result in the
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* following virtual address space:
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*
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* [L0 index] [L1 index] [L2 index] [L3 index] [page offset]
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* 1 bit 11 bits 11 bits 11 bits 14 bits
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*
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* To simplify things we only allow 32MB mappings directly from
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* the L2 tables such that in m1n1 all virtual addresses will look like this
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* instead (Block maps from L0 or L1 are not possible with 16KB pages):
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*
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* [L0 index] [L1 index] [L2 index] [page offset]
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* 1 bit 11 bits 11 bits 25 bits
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*
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* We initalize two L1 tables which cover the entire virtual memory space,
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* point to them in the singe L0 table and then create L2 tables on demand.
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*/
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#define VADDR_PAGE_OFFSET_BITS 25
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#define VADDR_L2_INDEX_BITS 11
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#define VADDR_L1_INDEX_BITS 11
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#define VADDR_L0_INDEX_BITS 1
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#define MAX_L2_TABLES 10
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#define ENTRIES_PER_TABLE 2048
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#define L2_PAGE_SIZE 0x2000000
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static uint64_t __pagetable_L0[2] ALIGNED(PAGE_SIZE);
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static uint64_t __pagetable_L1[2][ENTRIES_PER_TABLE] ALIGNED(PAGE_SIZE);
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static uint64_t __pagetable_L2[MAX_L2_TABLES][ENTRIES_PER_TABLE] ALIGNED(PAGE_SIZE);
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static uint32_t __pagetable_L2_next = 0;
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static uint64_t _mmu_make_block_pte(uintptr_t addr, uint8_t attribute_index)
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{
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uint64_t pte = PTE_TYPE_BLOCK;
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pte |= addr;
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pte |= PTE_FLAG_ACCESS;
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pte |= PTE_MAIR_INDEX(attribute_index);
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return pte;
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}
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static uint64_t _mmu_make_table_pte(uint64_t *addr)
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{
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uint64_t pte = PTE_TYPE_TABLE;
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pte |= (uintptr_t)addr;
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pte |= PTE_FLAG_ACCESS;
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return pte;
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}
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static void _mmu_init_pagetables(void)
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{
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memset64(__pagetable_L0, 0, sizeof __pagetable_L0);
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memset64(__pagetable_L1, 0, sizeof __pagetable_L1);
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memset64(__pagetable_L2, 0, sizeof __pagetable_L2);
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__pagetable_L0[0] = _mmu_make_table_pte(&__pagetable_L1[0][0]);
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__pagetable_L0[1] = _mmu_make_table_pte(&__pagetable_L1[1][0]);
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}
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static uint64_t _mmu_extract_L0_index(uintptr_t addr)
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{
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addr >>= VADDR_PAGE_OFFSET_BITS;
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addr >>= VADDR_L2_INDEX_BITS;
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addr >>= VADDR_L1_INDEX_BITS;
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addr &= (1 << VADDR_L0_INDEX_BITS) - 1;
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return (uint8_t)addr;
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}
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static uint64_t _mmu_extract_L1_index(uintptr_t addr)
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{
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addr >>= VADDR_PAGE_OFFSET_BITS;
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addr >>= VADDR_L2_INDEX_BITS;
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addr &= (1 << VADDR_L1_INDEX_BITS) - 1;
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return (uint32_t)addr;
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}
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static uint64_t _mmu_extract_L2_index(uintptr_t addr)
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{
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addr >>= VADDR_PAGE_OFFSET_BITS;
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addr &= (1 << VADDR_L2_INDEX_BITS) - 1;
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return (uint32_t)addr;
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}
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static uintptr_t _mmu_extract_addr(uint64_t pte)
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{
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// https://armv8-ref.codingbelief.com/en/chapter_d4/d43_1_vmsav8-64_translation_table_descriptor_formats.html
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// need to extract bits [47:14]
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pte &= ((1ULL << 48) - 1);
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pte &= ~((1ULL << 14) - 1);
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return (uintptr_t)pte;
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}
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static uint64_t *_mmu_get_L1_table(uintptr_t addr)
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{
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return __pagetable_L1[_mmu_extract_L0_index(addr)];
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}
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static uint64_t *_mmu_get_L2_table(uintptr_t addr)
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{
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uint64_t *tbl_l1 = _mmu_get_L1_table(addr);
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uint64_t l1_idx = _mmu_extract_L1_index(addr);
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uint64_t desc_l1 = tbl_l1[l1_idx];
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if (desc_l1 == 0) {
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if (__pagetable_L2_next == MAX_L2_TABLES)
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panic("MMU: not enough space to create an additional L2 table to "
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"map %lx",
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addr);
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desc_l1 = _mmu_make_table_pte(
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(uint64_t *)&__pagetable_L2[__pagetable_L2_next++]);
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tbl_l1[l1_idx] = desc_l1;
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}
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return (uint64_t *)_mmu_extract_addr(desc_l1);
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}
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static void _mmu_add_single_mapping(uintptr_t from, uintptr_t to,
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uint8_t attribute_index)
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{
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uint64_t *tbl_l2 = _mmu_get_L2_table(from);
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uint64_t l2_idx = _mmu_extract_L2_index(from);
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if (tbl_l2[l2_idx])
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panic("MMU: mapping for %lx already exists", from);
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tbl_l2[l2_idx] = _mmu_make_block_pte(to, attribute_index);
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}
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static void _mmu_add_mapping(uintptr_t from, uintptr_t to, size_t size,
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uint8_t attribute_index)
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{
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if (from % L2_PAGE_SIZE)
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panic("_mmu_add_mapping: from address not aligned: %lx", from);
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if (to % L2_PAGE_SIZE)
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panic("_mmu_add_mapping: to address not aligned: %lx", to);
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if (size % L2_PAGE_SIZE)
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panic("_mmu_add_mapping: size not aligned: %lx", size);
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while (size > 0) {
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_mmu_add_single_mapping(from, to, attribute_index);
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from += L2_PAGE_SIZE;
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to += L2_PAGE_SIZE;
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size -= L2_PAGE_SIZE;
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}
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}
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static void _mmu_add_default_mappings(void)
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{
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/* create MMIO mapping as both nGnRnE (identity) and nGnRE (starting at
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* 0xf0_0000_0000)
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*/
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_mmu_add_mapping(0x0000000000, 0x0000000000, 0x0800000000,
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MAIR_INDEX_DEVICE_nGnRnE);
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_mmu_add_mapping(0xf000000000, 0x0000000000, 0x0800000000,
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MAIR_INDEX_DEVICE_nGnRE);
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/* create identity mapping for 16GB RAM from 0x08_0000_0000 to
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* 0x0c_0000_0000 */
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_mmu_add_mapping(0x0800000000, 0x0800000000, 0x0400000000,
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MAIR_INDEX_NORMAL);
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}
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static void _mmu_configure(void)
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{
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msr(MAIR_EL2, (MAIR_ATTR_NORMAL_DEFAULT << MAIR_SHIFT_NORMAL) |
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(MAIR_ATTR_DEVICE_nGnRnE << MAIR_SHIFT_DEVICE_nGnRnE) |
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(MAIR_ATTR_DEVICE_nGnRE << MAIR_SHIFT_DEVICE_nGnRE));
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msr(TCR_EL2, TG0_16K | PS_1TB);
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msr(TTBR0_EL2, (uintptr_t)__pagetable_L0);
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// Armv8-A Address Translation, 100940_0101_en, page 28
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sysop("dsb ishst");
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sysop("tlbi vmalls12e1is");
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sysop("dsb ish");
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sysop("isb");
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}
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void mmu_init(void)
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{
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printf("MMU: Initializing...\n");
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_mmu_init_pagetables();
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_mmu_add_default_mappings();
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_mmu_configure();
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uint64_t sctl_old = read_sctl();
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uint64_t sctl_new = sctl_old | SCTL_I | SCTL_C | SCTL_M;
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printf("MMU: SCTL_EL2: %x -> %x\n", sctl_old, sctl_new);
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write_sctl(sctl_new);
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printf("MMU: running with MMU and caches enabled!\n");
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}
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void mmu_shutdown(void)
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{
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// FIXME: do we need to flush caches here?
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printf("MMU: shutting down...\n");
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write_sctl(read_sctl() & ~(SCTL_I | SCTL_C | SCTL_M));
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printf("MMU: shutdown successful.\n");
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}
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@ -66,4 +66,6 @@ void dc_cvac_range(void *addr, size_t length);
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void dc_cvau_range(void *addr, size_t length);
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void dc_civac_range(void *addr, size_t length);
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void mmu_init(void);
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void mmu_shutdown(void);
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#endif
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