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experiments/dmp.py: DMP/GoFetch bug test experiment
Signed-off-by: Hector Martin <marcan@marcan.st>
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Hector Martin
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219
proxyclient/experiments/dmp.py
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proxyclient/experiments/dmp.py
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#!/usr/bin/env python3
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# SPDX-License-Identifier: MIT
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import sys, pathlib, time
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sys.path.append(str(pathlib.Path(__file__).resolve().parents[1]))
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from m1n1.setup import *
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from m1n1 import asm
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REPETITIONS = 64
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PAGE_SIZE = 16384
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TEST_ECORE = 1
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TEST_PCORE = 4
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L2_LINE_SIZE = 128
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PNRG_a = 75
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PRNG_m = 31337
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rnd_idx = 8
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def prng(x):
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return (PNRG_a * x) % PRNG_m
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SIZE_DATA_ARRAY = (PRNG_m * L2_LINE_SIZE)
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data_buf_addr = u.memalign(PAGE_SIZE, SIZE_DATA_ARRAY)
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p.memset64(data_buf_addr, 0x5555555555555555, SIZE_DATA_ARRAY)
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aop_addr = u.memalign(PAGE_SIZE, PAGE_SIZE)
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p.memset64(aop_addr, 0x5555555555555555, PAGE_SIZE)
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freq = u.mrs(CNTFRQ_EL0)
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code = u.malloc(0x1000)
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util = asm.ARMAsm("""
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test:
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dc civac, x0
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dc civac, x1
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isb sy
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mov x7, #0x8000
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1:
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add x2, x2, #1
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mul x2, x2, x2
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sub x7, x7, #1
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cbnz x7, 1b
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and x2, x2, #(15 << 60)
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add x1, x1, x2
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ldrb w2, [x1, #512]
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and x2, x2, #(15 << 60)
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add x0, x0, x2
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dsb sy
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isb
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mrs x9, S3_2_c15_c0_0 // PMC0_EL1
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isb
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ldr x2, [x0, x2]
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isb
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mrs x10, S3_2_c15_c0_0
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sub x5, x10, x9
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and x2, x2, #(15 << 60)
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mov x7, #0x4000
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1:
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add x2, x2, #1
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mul x2, x2, x2
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sub x7, x7, #1
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cbnz x7, 1b
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and x2, x2, #(15 << 60)
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dsb sy
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isb
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mrs x9, S3_2_c15_c0_0
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isb
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ldr x2, [x1, x2]
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isb
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mrs x10, S3_2_c15_c0_0
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sub x0, x10, x9
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isb sy
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lsl x5, x5, #32
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orr x0, x0, x5
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ret
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""", code)
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for i in util.disassemble():
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print(i)
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iface.writemem(code, util.data)
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p.dc_cvau(code, len(util.data))
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p.ic_ivau(code, len(util.data))
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# Set higher cpufreq pstate on all clusters
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p.cpufreq_init()
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p.smp_start_secondaries()
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p.smp_set_wfe_mode(True);
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def cpu_call(cpu, x, *args):
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return p.smp_call_sync(cpu, x | REGION_RX_EL1, *args)
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def init_core(cpu):
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p.mmu_init_secondary(cpu)
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def mrs(x):
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return u.mrs(x, call=lambda x, *args: cpu_call(cpu, x, *args))
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def msr(x, v):
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u.msr(x, v, call=lambda x, *args: cpu_call(cpu, x, *args))
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is_ecore = not (mrs(MPIDR_EL1) & (1 << 16))
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# Enable DC MVA ops
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v = mrs(EHID4_EL1 if is_ecore else HID4_EL1)
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v &= ~(1 << 11)
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msr(EHID4_EL1 if is_ecore else HID4_EL1, v)
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# Enable PMU
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v = mrs(PMCR0_EL1)
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v |= 1 | (1<<30)
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msr(PMCR0_EL1, v)
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msr(PMCR1_EL1, 0xffffffffffffffff)
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# Enable TBI
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v = mrs(TCR_EL1)
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v |= (1 << 37)
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msr(TCR_EL1, v)
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# Enable user cache ops
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v = mrs(SCTLR_EL1)
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v |= (1 << 26)
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msr(SCTLR_EL1, v)
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init_core(TEST_ECORE)
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init_core(TEST_PCORE)
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# Enable DC MVA ops
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v = u.mrs(EHID4_EL1)
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v &= ~(1 << 11)
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u.msr(EHID4_EL1, v)
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def test_cpu(cpu, mask):
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global rnd_idx
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total_aop = total_ptr = 0
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p.memset64(data_buf_addr, 0x5555555555555555, SIZE_DATA_ARRAY)
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p.memset64(aop_addr, 0x5555555555555555, PAGE_SIZE)
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for i in range(REPETITIONS):
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test_offset = L2_LINE_SIZE * rnd_idx
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test_addr = data_buf_addr + test_offset
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p.write64(aop_addr, test_addr | mask | REGION_RWX_EL0)
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p.dc_civac(aop_addr, L2_LINE_SIZE)
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# p.dc_civac(data_buf_addr, SIZE_DATA_ARRAY)
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elapsed = p.smp_call_sync_el0(cpu, util.test | REGION_RWX_EL0, aop_addr | REGION_RWX_EL0, test_addr | REGION_RWX_EL0, 7 << 60)
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time_aop = elapsed >> 32
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time_ptr = elapsed & 0xffffffff
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total_aop += time_aop
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total_ptr += time_ptr
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rnd_idx = prng(rnd_idx)
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return total_aop, total_ptr
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print("ECore plain:", test_cpu(TEST_ECORE, 0))
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print("ECore mask: ", test_cpu(TEST_ECORE, 0xaaaaaaaa00000000))
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print("PCore plain:", test_cpu(TEST_PCORE, 0))
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print("PCore mask: ", test_cpu(TEST_PCORE, 0xaaaaaaaa00000000))
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for reg in (
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# "HID0_EL1",
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# "HID1_EL1",
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# "HID2_EL1",
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# "HID3_EL1",
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"HID4_EL1",
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# "HID5_EL1",
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# "HID6_EL1",
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# "HID7_EL1",
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# "HID8_EL1",
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# "HID9_EL1",
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# "HID10_EL1",
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"HID11_EL1",
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# "HID13_EL1",
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# "HID14_EL1",
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# "HID16_EL1",
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# "HID17_EL1",
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# "HID18_EL1",
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"HID21_EL1",
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# "HID26_EL1",
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# "HID27_EL1",
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):
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cpu = TEST_PCORE
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hid = u.mrs(reg, call=lambda x, *args: cpu_call(cpu, x, *args))
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for i in range(64):
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if (reg, i) not in (
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("HID4_EL1", 4),
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("HID11_EL1", 30),
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("HID21_EL1", 40),
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):
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continue
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bit = (1 << i)
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print(f"Test {reg} bit {i}:", end=" ")
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u.msr(reg, hid ^ bit, call=lambda x, *args: cpu_call(cpu, x, *args))
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tval = test_cpu(cpu, 0)[1]
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control = test_cpu(cpu, 0xaaaaaaaa00000000)[1]
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if tval < (0.75 * control):
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print(f"DMP active {tval} {control}")
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else:
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print(f"DMP INACTIVE {tval} {control}")
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u.msr(reg, hid, call=lambda x, *args: cpu_call(cpu, x, *args))
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