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chickens: Add preliminary T6020 support

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Signed-off-by: Mario Hros <git@reversity.org>
This commit is contained in:
Mario Hros 2023-02-06 23:14:42 +01:00 committed by Hector Martin
parent afb68db34c
commit e71ad13474
3 changed files with 39 additions and 0 deletions
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14
src/chickens.c
View file

@ -18,6 +18,8 @@
#define MIDR_PART_T8110_AVALANCHE 0x31
#define MIDR_PART_T8112_BLIZZARD 0x32
#define MIDR_PART_T8112_AVALANCHE 0x33
#define MIDR_PART_T6020_BLIZZARD 0x34
#define MIDR_PART_T6020_AVALANCHE 0x35
#define MIDR_PART_T6021_BLIZZARD 0x38
#define MIDR_PART_T6021_AVALANCHE 0x39
@ -31,6 +33,8 @@ void init_t6000_firestorm(int rev);
void init_t6001_firestorm(int rev);
void init_t8112_blizzard(void);
void init_t8112_avalanche(int rev);
void init_t6020_blizzard(void);
void init_t6020_avalanche(int rev);
void init_t6021_blizzard(void);
void init_t6021_avalanche(int rev);
@ -93,6 +97,16 @@ const char *init_cpu(void)
init_t8112_blizzard();
break;
case MIDR_PART_T6020_AVALANCHE:
cpu = "M2 Pro Avalanche";
init_t6020_avalanche(rev);
break;
case MIDR_PART_T6020_BLIZZARD:
cpu = "M2 Pro Blizzard";
init_t6020_blizzard();
break;
case MIDR_PART_T6021_AVALANCHE:
cpu = "M2 Max Avalanche";
init_t6021_avalanche(rev);

14
src/chickens_avalanche.c
View file

@ -51,6 +51,20 @@ void init_t8112_avalanche(int rev)
}
}
void init_t6020_avalanche(int rev)
{
UNUSED(rev);
init_common_avalanche();
reg_mask(SYS_IMP_APL_HID3, HID3_DEV_PCIE_THROTTLE_LIMIT_MASK, HID3_DEV_PCIE_THROTTLE_LIMIT(62));
reg_set(SYS_IMP_APL_HID3, HID3_DEV_PCIE_THROTTLE_ENABLE);
reg_set(SYS_IMP_APL_HID18, HID18_AVL_UNK27 | HID18_AVL_UNK29);
reg_set(SYS_IMP_APL_HID16, HID16_AVL_UNK12);
reg_mask(SYS_IMP_APL_HID5, HID5_BLZ_UNK_19_18_MASK, HID5_BLZ_UNK18);
}
void init_t6021_avalanche(int rev)
{
UNUSED(rev);

11
src/chickens_blizzard.c
View file

@ -17,6 +17,17 @@ void init_t8112_blizzard(void)
reg_set(SYS_IMP_APL_EHID18, EHID18_BLZ_UNK34);
}
void init_t6020_blizzard(void)
{
init_common_blizzard();
reg_mask(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_LIMIT_MASK, EHID9_DEV_2_THROTTLE_LIMIT(62));
reg_set(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_ENABLE);
reg_set(SYS_IMP_APL_EHID18, EHID18_BLZ_UNK34);
reg_mask(SYS_IMP_APL_HID5, HID5_BLZ_UNK_19_18_MASK, HID5_BLZ_UNK18);
}
void init_t6021_blizzard(void)
{
init_common_blizzard();