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https://github.com/AsahiLinux/m1n1
synced 2024-11-21 22:23:05 +00:00
kboot_gpu: Add proper max-power and leakage calculations for t600x/t8103
Signed-off-by: Asahi Lina <lina@asahilina.net>
This commit is contained in:
Asahi Lina
Hector Martin
parent
057151cb21
commit
e6ffbb018b
2 changed files with 202 additions and 22 deletions
3
Makefile
3
Makefile
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@ -102,7 +102,7 @@ OBJECTS := \
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i2c.o \
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iodev.o \
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iova.o \
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kboot.o kboot_gpu.o \
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kboot.o \
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main.o \
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mcc.o \
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memory.o memory_asm.o \
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@ -130,6 +130,7 @@ OBJECTS := \
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$(MINILZLIB_OBJECTS) $(TINF_OBJECTS) $(DLMALLOC_OBJECTS) $(LIBFDT_OBJECTS) $(RUST_LIBS)
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FP_OBJECTS := \
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kboot_gpu.o \
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math/expf.o \
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math/exp2f_data.o \
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221
src/kboot_gpu.c
221
src/kboot_gpu.c
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@ -3,6 +3,8 @@
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#include "kboot.h"
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#include "adt.h"
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#include "assert.h"
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#include "math.h"
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#include "pmgr.h"
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#include "soc.h"
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#include "utils.h"
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@ -22,29 +24,97 @@ struct perf_state {
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u32 volt;
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};
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static int get_core_counts(u32 *count, u32 nclusters, u32 ncores)
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{
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u64 base;
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pmgr_adt_power_enable("/arm-io/sgx");
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int adt_sgx_path[8];
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if (adt_path_offset_trace(adt, "/arm-io/sgx", adt_sgx_path) < 0)
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bail("ADT: GPU: Failed to get sgx\n");
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if (adt_get_reg(adt, adt_sgx_path, "reg", 0, &base, NULL) < 0)
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bail("ADT: GPU: Failed to get sgx reg 0\n");
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u32 cores_lo = read32(base + 0xd01500);
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u32 cores_hi = read32(base + 0xd01514);
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u64 cores = (((u64)cores_hi) << 32) | cores_lo;
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for (u32 i = 0; i < nclusters; i++) {
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count[i] = __builtin_popcount(cores & MASK(ncores));
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cores >>= ncores;
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}
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return 0;
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}
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static void adjust_leakage(float *val, u32 clusters, u32 *cores, u32 max, float uncore_fraction)
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{
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for (u32 i = 0; i < clusters; i++) {
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float uncore = val[i] * uncore_fraction;
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float core = val[i] - uncore;
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val[i] = uncore + (cores[i] / (float)max) * core;
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}
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}
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static void load_fuses(float *out, u32 count, u64 base, u32 start, u32 width, float scale,
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float offset, bool flip)
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{
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for (u32 i = 0; i < count; i++) {
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base += (start / 32) * 4;
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start &= 31;
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u32 low = read32(base);
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u32 high = read32(base + 4);
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u32 val = (((((u64)high) << 32) | low) >> start) & MASK(width);
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float fval = (float)val * scale + offset;
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if (flip)
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out[count - i - 1] = fval;
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else
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out[i] = fval;
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start += width;
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}
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}
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static u32 t8103_pwr_scale[] = {0, 63, 80, 108, 150, 198, 210};
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// TODO this isn't a static table any more
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static u32 t8112_pwr_scale[] = {0, 66, 92, 119, 153, 184, 214, 240, 240};
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static int calc_power_t81xx(int sgx, u32 count, u32 table_count,
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const struct perf_state *perf_states, u32 *max_pwr)
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static int calc_power_t81xx(u32 count, u32 table_count, const struct perf_state *core,
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const struct perf_state *sram, u32 *max_pwr, float *core_leak,
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float *sram_leak)
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{
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UNUSED(sgx);
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UNUSED(sram);
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UNUSED(core_leak);
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UNUSED(sram_leak);
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u32 *pwr_scale;
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u32 pwr_scale_count;
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u32 core_count;
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u32 max_cores;
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switch (chip_id) {
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case T8103:
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pwr_scale = t8103_pwr_scale;
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pwr_scale_count = ARRAY_SIZE(t8103_pwr_scale);
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max_cores = 8;
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break;
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case T8112:
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pwr_scale = t8112_pwr_scale;
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pwr_scale_count = ARRAY_SIZE(t8112_pwr_scale);
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break;
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default:
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bail("ADT: GPU: Unsupported chip\n");
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}
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if (get_core_counts(&core_count, 1, max_cores))
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return -1;
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if (table_count != 1)
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bail("ADT: GPU: expected 1 perf state table but got %d\n", table_count);
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@ -52,19 +122,31 @@ static int calc_power_t81xx(int sgx, u32 count, u32 table_count,
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bail("ADT: GPU: expected %d perf states but got %d\n", pwr_scale_count, count);
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for (u32 i = 0; i < pwr_scale_count; i++)
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max_pwr[i] = (u32)perf_states[i].volt * (u32)pwr_scale[i] * 100;
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max_pwr[i] = (u32)core[i].volt * (u32)pwr_scale[i] * 100;
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core_leak[0] = 1000.0;
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sram_leak[0] = 45.0;
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adjust_leakage(core_leak, 1, &core_count, max_cores, 0.12);
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adjust_leakage(sram_leak, 1, &core_count, max_cores, 0.2);
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return 0;
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}
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// TODO
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static u32 t6000_pwr_scale[] = {0, 15, 19, 25, 34, 50, 100};
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static int calc_power_t600x(int sgx, u32 count, u32 table_count,
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const struct perf_state *perf_states, u32 *max_pwr)
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static int calc_power_t600x(u32 count, u32 table_count, const struct perf_state *core,
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const struct perf_state *sram, u32 *max_pwr, float *core_leak,
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float *sram_leak)
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{
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UNUSED(sgx);
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UNUSED(perf_states);
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const float s_sram = 4.3547606;
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const float k_sram = 0.024927923;
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// macOS difference: macOS uses a misbehaved piecewise function here
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// Since it's obviously wrong, let's just use only the first component
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const float s_core = 1.48461742;
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const float k_core = 0.39013552;
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const float dk_core = 8.558;
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const float dk_sram = 0.05;
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u32 nclusters = 0;
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switch (chip_id) {
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@ -79,16 +161,64 @@ static int calc_power_t600x(int sgx, u32 count, u32 table_count,
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break;
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}
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u32 pwr_scale_count = ARRAY_SIZE(t6000_pwr_scale);
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u32 core_count[MAX_CLUSTERS];
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if (get_core_counts(core_count, nclusters, 8))
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return -1;
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load_fuses(core_leak + 0, min(4, nclusters), 0x2922bc1b8, 25, 13, 2, 2, false);
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load_fuses(sram_leak + 0, min(4, nclusters), 0x2922bc1cc, 4, 9, 1, 1, false);
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if (nclusters == 8) {
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load_fuses(core_leak + 4, 4, 0x22922bc1b8, 25, 13, 2, 2, true);
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load_fuses(sram_leak + 4, 4, 0x22922bc1cc, 4, 9, 1, 1, true);
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}
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printf("FDT: GPU: Core counts: ");
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for (u32 i = 0; i < nclusters; i++) {
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printf("%d ", core_count[i]);
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}
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printf("\n");
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adjust_leakage(core_leak, nclusters, core_count, 8, 0.0825);
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adjust_leakage(sram_leak, nclusters, core_count, 8, 0.2247);
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if (table_count != nclusters)
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bail("ADT: GPU: expected %d perf state tables but got %d\n", nclusters, table_count);
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if (count != pwr_scale_count)
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bail("ADT: GPU: expected %d perf states but got %d\n", pwr_scale_count, count);
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max_pwr[0] = 0;
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for (u32 i = 0; i < pwr_scale_count; i++) {
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max_pwr[i] = t6000_pwr_scale[i] * 1667430 * nclusters / 8;
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for (u32 i = 1; i < count; i++) {
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u32 total_mw = 0;
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for (u32 j = 0; j < nclusters; j++) {
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// macOS difference: macOS truncates Hz to integer MHz before doing this math.
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// That's probably wrong, so let's not do that.
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float mw = 0;
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size_t idx = j * count + i;
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mw += sram[idx].volt / 1000.f * sram_leak[j] * k_sram *
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expf(sram[idx].volt / 1000.f * s_sram);
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mw += core[idx].volt / 1000.f * core_leak[j] * k_core *
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expf(core[idx].volt / 1000.f * s_core);
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float sbase = sram[idx].volt / 750.f;
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float sram_v_p = sbase * sbase * sbase;
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mw += dk_sram * (sram[idx].freq / 1000000.f) * sram_v_p;
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float cbase = core[idx].volt / 750.f;
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float core_v_p;
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if (core[idx].volt > 750)
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core_v_p = cbase * cbase * cbase; // v ^ 3
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else
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core_v_p = cbase * cbase; // v ^ 2
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mw += dk_core * (core[idx].freq / 1000000.f) * core_v_p;
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total_mw += mw;
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}
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max_pwr[i] = total_mw * 1000;
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}
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return 0;
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@ -122,10 +252,31 @@ static int dt_set_region(void *dt, int sgx, const char *name, const char *path)
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return 0;
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}
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int fdt_set_float_array(void *dt, int node, const char *name, float *val, int count)
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{
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fdt32_t data[MAX_CLUSTERS];
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if (count > MAX_CLUSTERS)
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bail("FDT: GPU: fdt_set_float_array() with too many values\n");
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memcpy(data, val, sizeof(float) * count);
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for (int i = 0; i < count; i++) {
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data[i] = cpu_to_fdt32(data[i]);
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}
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if (fdt_setprop_inplace(dt, node, name, data, sizeof(u32) * count))
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bail("FDT: GPU: Failed to set %s\n", name);
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return 0;
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}
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int dt_set_gpu(void *dt)
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{
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int (*calc_power)(int sgx, u32 count, u32 table_count, const struct perf_state *perf,
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u32 *max_pwr);
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int (*calc_power)(u32 count, u32 table_count, const struct perf_state *perf,
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const struct perf_state *sram, u32 *max_pwr, float *core_leak,
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float *sram_leak);
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printf("FDT: GPU: Initializing GPU info\n");
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switch (chip_id) {
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case T8103:
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@ -177,16 +328,44 @@ int dt_set_gpu(void *dt)
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bail("ADT: GPU: perf-state-table-count too large\n");
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u32 perf_states_len;
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const struct perf_state *perf_states;
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const struct perf_state *perf_states, *perf_states_sram;
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perf_states = adt_getprop(adt, sgx, "perf-states", &perf_states_len);
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if (!perf_states ||
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perf_states_len != sizeof(*perf_states) * perf_state_count * perf_state_table_count)
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bail("ADT: GPU: invalid perf-states length\n");
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u32 max_pwr[MAX_PSTATES];
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perf_states_sram = adt_getprop(adt, sgx, "perf-states-sram", &perf_states_len);
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if (perf_states_sram &&
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perf_states_len != sizeof(*perf_states) * perf_state_count * perf_state_table_count)
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bail("ADT: GPU: invalid perf-states-sram length\n");
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if (calc_power(sgx, perf_state_count, perf_state_table_count, perf_states, max_pwr))
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u32 max_pwr[MAX_PSTATES];
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float core_leak[MAX_CLUSTERS];
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float sram_leak[MAX_CLUSTERS];
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if (calc_power(perf_state_count, perf_state_table_count, perf_states, perf_states_sram, max_pwr,
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core_leak, sram_leak))
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return -1;
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printf("FDT: GPU: Max power table: ");
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for (u32 i = 0; i < perf_state_count; i++) {
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printf("%d ", max_pwr[i]);
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}
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printf("\nFDT: GPU: Core leakage table: ");
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for (u32 i = 0; i < perf_state_table_count; i++) {
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printf("%d.%03d ", (int)core_leak[i], ((int)(core_leak[i] * 1000) % 1000));
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}
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printf("\nFDT: GPU: SRAM leakage table: ");
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for (u32 i = 0; i < perf_state_table_count; i++) {
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printf("%d.%03d ", (int)sram_leak[i], ((int)(sram_leak[i] * 1000) % 1000));
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}
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printf("\n");
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if (fdt_set_float_array(dt, gpu, "apple,core-leak-coef", core_leak, perf_state_table_count))
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return -1;
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if (fdt_set_float_array(dt, gpu, "apple,sram-leak-coef", sram_leak, perf_state_table_count))
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return -1;
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u32 i = 0;
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