m1n1.utils: Introduce Reloadable class for magic live-reloading

Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin 2021-06-17 20:34:54 +09:00
parent 2f68012d6c
commit e218129931
4 changed files with 14 additions and 8 deletions

View file

@ -57,7 +57,7 @@ class TraceMode(IntEnum):
HOOK = 4 HOOK = 4
RESERVED = 5 RESERVED = 5
class HV: class HV(Reloadable):
PTE_VALID = 1 << 0 PTE_VALID = 1 << 0
PTE_MEMATTR_UNCHANGED = 0b1111 << 2 PTE_MEMATTR_UNCHANGED = 0b1111 << 2

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@ -81,7 +81,7 @@ ExcInfo = Struct(
"data" / Int64ul, "data" / Int64ul,
) )
class UartInterface: class UartInterface(Reloadable):
REQ_NOP = 0x00AA55FF REQ_NOP = 0x00AA55FF
REQ_PROXY = 0x01AA55FF REQ_PROXY = 0x01AA55FF
REQ_MEMREAD = 0x02AA55FF REQ_MEMREAD = 0x02AA55FF
@ -426,7 +426,7 @@ REGION_RWX_EL0 = 0x8000000000
REGION_RW_EL0 = 0x9000000000 REGION_RW_EL0 = 0x9000000000
REGION_RX_EL1 = 0xa000000000 REGION_RX_EL1 = 0xa000000000
class M1N1Proxy: class M1N1Proxy(Reloadable):
S_OK = 0 S_OK = 0
S_BADCMD = -1 S_BADCMD = -1

View file

@ -5,6 +5,7 @@ from construct import *
from .asm import ARMAsm from .asm import ARMAsm
from .proxy import * from .proxy import *
from .utils import Reloadable
from .tgtypes import * from .tgtypes import *
from .sysreg import * from .sysreg import *
from .malloc import Heap from .malloc import Heap
@ -18,7 +19,7 @@ SIMD_S = Array(32, Array(4, Int32ul))
SIMD_D = Array(32, Array(2, Int64ul)) SIMD_D = Array(32, Array(2, Int64ul))
SIMD_Q = Array(32, BytesInteger(16, swapped=True)) SIMD_Q = Array(32, BytesInteger(16, swapped=True))
class ProxyUtils(object): class ProxyUtils(Reloadable):
CODE_BUFFER_SIZE = 0x10000 CODE_BUFFER_SIZE = 0x10000
def __init__(self, p, heap_size=1024 * 1024 * 1024): def __init__(self, p, heap_size=1024 * 1024 * 1024):
self.iface = p.iface self.iface = p.iface

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@ -1,6 +1,6 @@
# SPDX-License-Identifier: MIT # SPDX-License-Identifier: MIT
from enum import Enum from enum import Enum
import bisect, copy, heapq import bisect, copy, heapq, importlib, sys
from construct import Adapter, Int64ul, Int32ul, Int16ul, Int8ul from construct import Adapter, Int64ul, Int32ul, Int16ul, Int8ul
__all__ = [] __all__ = []
@ -53,7 +53,12 @@ def chexdump32(s, st=0, abbreviate=True):
last = val last = val
skip = False skip = False
class Register: class Reloadable:
def _reloadme(self):
mod = importlib.reload(sys.modules[self.__class__.__module__])
self.__class__ = getattr(mod, self.__class__.__name__)
class Register(Reloadable):
def __init__(self, v=0, **kwargs): def __init__(self, v=0, **kwargs):
self._value = v self._value = v
self._fields_list = [k for k in self.__class__.__dict__ if not k.startswith("_")] self._fields_list = [k for k in self.__class__.__dict__ if not k.startswith("_")]
@ -175,7 +180,7 @@ class RegAdapter(Adapter):
def _encode(self, obj, context, path): def _encode(self, obj, context, path):
return obj.value return obj.value
class RangeMap: class RangeMap(Reloadable):
def __init__(self): def __init__(self):
self.__start = [] self.__start = []
self.__end = [] self.__end = []
@ -542,7 +547,7 @@ class RegArrayAccessor:
else: else:
return [self.rd(self.addr + i) for i in self.range[item]] return [self.rd(self.addr + i) for i in self.range[item]]
class RegMap(metaclass=RegMeta): class RegMap(Reloadable, metaclass=RegMeta):
def __init__(self, backend, base): def __init__(self, backend, base):
self._base = base self._base = base
self._backend = backend self._backend = backend