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https://github.com/AsahiLinux/m1n1
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m1n1.utils: Introduce Reloadable class for magic live-reloading
Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
parent
2f68012d6c
commit
e218129931
4 changed files with 14 additions and 8 deletions
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@ -57,7 +57,7 @@ class TraceMode(IntEnum):
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HOOK = 4
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HOOK = 4
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RESERVED = 5
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RESERVED = 5
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class HV:
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class HV(Reloadable):
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PTE_VALID = 1 << 0
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PTE_VALID = 1 << 0
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PTE_MEMATTR_UNCHANGED = 0b1111 << 2
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PTE_MEMATTR_UNCHANGED = 0b1111 << 2
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@ -81,7 +81,7 @@ ExcInfo = Struct(
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"data" / Int64ul,
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"data" / Int64ul,
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)
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)
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class UartInterface:
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class UartInterface(Reloadable):
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REQ_NOP = 0x00AA55FF
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REQ_NOP = 0x00AA55FF
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REQ_PROXY = 0x01AA55FF
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REQ_PROXY = 0x01AA55FF
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REQ_MEMREAD = 0x02AA55FF
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REQ_MEMREAD = 0x02AA55FF
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@ -426,7 +426,7 @@ REGION_RWX_EL0 = 0x8000000000
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REGION_RW_EL0 = 0x9000000000
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REGION_RW_EL0 = 0x9000000000
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REGION_RX_EL1 = 0xa000000000
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REGION_RX_EL1 = 0xa000000000
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class M1N1Proxy:
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class M1N1Proxy(Reloadable):
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S_OK = 0
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S_OK = 0
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S_BADCMD = -1
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S_BADCMD = -1
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@ -5,6 +5,7 @@ from construct import *
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from .asm import ARMAsm
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from .asm import ARMAsm
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from .proxy import *
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from .proxy import *
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from .utils import Reloadable
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from .tgtypes import *
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from .tgtypes import *
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from .sysreg import *
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from .sysreg import *
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from .malloc import Heap
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from .malloc import Heap
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@ -18,7 +19,7 @@ SIMD_S = Array(32, Array(4, Int32ul))
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SIMD_D = Array(32, Array(2, Int64ul))
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SIMD_D = Array(32, Array(2, Int64ul))
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SIMD_Q = Array(32, BytesInteger(16, swapped=True))
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SIMD_Q = Array(32, BytesInteger(16, swapped=True))
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class ProxyUtils(object):
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class ProxyUtils(Reloadable):
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CODE_BUFFER_SIZE = 0x10000
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CODE_BUFFER_SIZE = 0x10000
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def __init__(self, p, heap_size=1024 * 1024 * 1024):
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def __init__(self, p, heap_size=1024 * 1024 * 1024):
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self.iface = p.iface
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self.iface = p.iface
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@ -1,6 +1,6 @@
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# SPDX-License-Identifier: MIT
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# SPDX-License-Identifier: MIT
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from enum import Enum
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from enum import Enum
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import bisect, copy, heapq
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import bisect, copy, heapq, importlib, sys
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from construct import Adapter, Int64ul, Int32ul, Int16ul, Int8ul
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from construct import Adapter, Int64ul, Int32ul, Int16ul, Int8ul
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__all__ = []
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__all__ = []
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@ -53,7 +53,12 @@ def chexdump32(s, st=0, abbreviate=True):
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last = val
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last = val
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skip = False
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skip = False
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class Register:
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class Reloadable:
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def _reloadme(self):
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mod = importlib.reload(sys.modules[self.__class__.__module__])
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self.__class__ = getattr(mod, self.__class__.__name__)
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class Register(Reloadable):
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def __init__(self, v=0, **kwargs):
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def __init__(self, v=0, **kwargs):
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self._value = v
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self._value = v
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self._fields_list = [k for k in self.__class__.__dict__ if not k.startswith("_")]
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self._fields_list = [k for k in self.__class__.__dict__ if not k.startswith("_")]
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@ -175,7 +180,7 @@ class RegAdapter(Adapter):
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def _encode(self, obj, context, path):
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def _encode(self, obj, context, path):
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return obj.value
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return obj.value
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class RangeMap:
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class RangeMap(Reloadable):
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def __init__(self):
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def __init__(self):
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self.__start = []
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self.__start = []
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self.__end = []
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self.__end = []
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@ -542,7 +547,7 @@ class RegArrayAccessor:
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else:
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else:
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return [self.rd(self.addr + i) for i in self.range[item]]
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return [self.rd(self.addr + i) for i in self.range[item]]
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class RegMap(metaclass=RegMeta):
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class RegMap(Reloadable, metaclass=RegMeta):
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def __init__(self, backend, base):
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def __init__(self, backend, base):
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self._base = base
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self._base = base
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self._backend = backend
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self._backend = backend
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