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m1n1.hv: Fix register names

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Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin 2023-05-21 12:28:43 +09:00
parent 076217a802
commit db598aa4cf
2 changed files with 3 additions and 3 deletions
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4
proxyclient/m1n1/hv/__init__.py
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@ -1429,9 +1429,9 @@ class HV(Reloadable):
self.u.msr(MDSCR_EL1, MDSCR(MDE=1).value) self.u.msr(MDSCR_EL1, MDSCR(MDE=1).value)
# Enable AMX # Enable AMX
amx_ctl = AMX_CTL(self.u.mrs(AMX_CTL_EL1)) amx_ctl = AMX_CONFIG(self.u.mrs(AMX_CONFIG_EL1))
amx_ctl.EN_EL1 = 1 amx_ctl.EN_EL1 = 1
self.u.msr(AMX_CTL_EL1, amx_ctl.value) self.u.msr(AMX_CONFIG_EL1, amx_ctl.value)
# Set guest AP keys # Set guest AP keys
self.u.msr(VMKEYLO_EL2, 0x4E7672476F6E6147) self.u.msr(VMKEYLO_EL2, 0x4E7672476F6E6147)

2
proxyclient/m1n1/sysreg.py
View file

@ -291,7 +291,7 @@ class HACR(Register64):
TRAP_UPM = 58 TRAP_UPM = 58
TRAP_s3_1z7_c15_cx_3 = 59 TRAP_s3_1z7_c15_cx_3 = 59
class AMX_CTL(Register64): class AMX_CONFIG(Register64):
EN = 63 EN = 63
EN_EL1 = 62 EN_EL1 = 62