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https://github.com/AsahiLinux/m1n1
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memory: Only map available RAM
We saw some crazy speculation running in the HV breaking things by reading from invalid RAM, so let's actually map only what's available. For now we do map all lowmem as we haven't seen SErrors there yet, but we stop at the high boundary. Fixes: #97 Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin
parent
7a29455646
commit
da024ffbd8
3 changed files with 61 additions and 42 deletions
5
src/fb.c
5
src/fb.c
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@ -4,6 +4,7 @@
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#include "assert.h"
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#include "iodev.h"
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#include "malloc.h"
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#include "memory.h"
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#include "string.h"
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#include "types.h"
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#include "utils.h"
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@ -306,6 +307,10 @@ void fb_init(void)
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fb.depth = cur_boot_args.video.depth & FB_DEPTH_MASK;
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printf("fb init: %dx%d (%d) [s=%d] @%p\n", fb.width, fb.height, fb.depth, fb.stride, fb.ptr);
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uint64_t fb_size = cur_boot_args.video.stride * cur_boot_args.video.height;
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mmu_add_mapping(cur_boot_args.video.base, cur_boot_args.video.base, ALIGN_UP(fb_size, 0x4000),
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MAIR_IDX_NORMAL, PERM_RWX);
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if (cur_boot_args.video.depth & FB_DEPTH_FLAG_RETINA) {
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logo = &logo_256;
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console.font.ptr = _binary_build_font_retina_bin_start;
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63
src/memory.c
63
src/memory.c
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@ -9,6 +9,7 @@
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#include "smp.h"
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#include "string.h"
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#include "utils.h"
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#include "xnuboot.h"
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#define PAGE_SIZE 0x4000
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#define CACHE_LINE_SIZE 64
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@ -47,36 +48,6 @@ static inline void write_sctlr(u64 val)
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sysop("isb");
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}
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/*
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* https://armv8-ref.codingbelief.com/en/chapter_d4/d43_2_armv8_translation_table_level_3_descriptor_formats.html
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* PTE_TYPE:PTE_BLOCK indicates that the page table entry (PTE) points to a physical memory block
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* PTE_TYPE:PTE_TABLE indicates that the PTE points to another PTE
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* PTE_TYPE:PTE_PAGE indicates that the PTE points to a single page
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* PTE_FLAG_ACCESS is required to allow access to the memory region
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* PTE_MAIR_IDX sets the MAIR index to be used for this PTE
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*/
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#define PTE_VALID BIT(0)
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#define PTE_TYPE BIT(1)
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#define PTE_BLOCK 0
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#define PTE_TABLE 1
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#define PTE_PAGE 1
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#define PTE_ACCESS BIT(10)
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#define PTE_MAIR_IDX(i) ((i & 7) << 2)
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#define PTE_PXN BIT(53)
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#define PTE_UXN BIT(54)
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#define PTE_AP_RO BIT(7)
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#define PTE_AP_EL0 BIT(6)
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#define PERM_RO_EL0 PTE_AP_EL0 | PTE_AP_RO | PTE_PXN | PTE_UXN
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#define PERM_RW_EL0 PTE_AP_EL0 | PTE_PXN | PTE_UXN
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#define PERM_RX_EL0 PTE_AP_EL0 | PTE_AP_RO
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#define PERM_RWX_EL0 PTE_AP_EL0
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#define PERM_RO PTE_AP_RO | PTE_PXN | PTE_UXN
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#define PERM_RW PTE_PXN | PTE_UXN
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#define PERM_RX PTE_AP_RO | PTE_UXN
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#define PERM_RWX 0
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#define VADDR_L3_INDEX_BITS 11
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#define VADDR_L2_INDEX_BITS 11
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// We treat two concatenated L1 page tables as one
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@ -171,9 +142,6 @@ enum SPRR_val_t {
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* contains a field to select one of these which will then be used
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* to select the corresponding memory access flags from MAIR.
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*/
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#define MAIR_IDX_NORMAL 0
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#define MAIR_IDX_DEVICE_nGnRnE 1
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#define MAIR_IDX_DEVICE_nGnRE 2
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#define MAIR_SHIFT_NORMAL (MAIR_IDX_NORMAL * 8)
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#define MAIR_SHIFT_DEVICE_nGnRnE (MAIR_IDX_DEVICE_nGnRnE * 8)
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@ -326,11 +294,16 @@ static void mmu_init_pagetables(void)
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mmu_pt_L0[1] = mmu_make_table_pte(&mmu_pt_L1[ENTRIES_PER_L1_TABLE >> 1]);
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}
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static void mmu_add_mapping(u64 from, u64 to, size_t size, u8 attribute_index, u64 perms)
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void mmu_add_mapping(u64 from, u64 to, size_t size, u8 attribute_index, u64 perms)
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{
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if (mmu_map(from, to | PTE_MAIR_IDX(attribute_index) | PTE_ACCESS | PTE_VALID | perms, size) <
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0)
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panic("Failed to add MMU mapping 0x%lx -> 0x%lx (0x%lx)\n", from, to, size);
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sysop("dsb ishst");
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sysop("tlbi vmalle1is");
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sysop("dsb ish");
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sysop("isb");
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}
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static void mmu_rm_mapping(u64 from, size_t size)
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@ -352,11 +325,17 @@ static void mmu_add_default_mappings(void)
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mmu_add_mapping(0x0680000000, 0x0680000000, 0x0020000000, MAIR_IDX_DEVICE_nGnRnE, PERM_RW_EL0);
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mmu_add_mapping(0x06a0000000, 0x06a0000000, 0x0060000000, MAIR_IDX_DEVICE_nGnRE, PERM_RW_EL0);
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uint64_t ram_size = cur_boot_args.mem_size + cur_boot_args.phys_base - 0x0800000000;
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ram_size = ALIGN_DOWN(ram_size, 0x4000);
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printf("Top of RAM: 0x%lx\n", ram_size);
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/*
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* Create identity mapping for 16GB RAM from 0x08_0000_0000 to 0x0c_0000_0000
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* Create identity mapping for RAM from 0x08_0000_0000
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* With SPRR enabled, this becomes RW.
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*/
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mmu_add_mapping(0x0800000000, 0x0800000000, 0x0400000000, MAIR_IDX_NORMAL, PERM_RWX);
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mmu_add_mapping(0x0800000000, 0x0800000000, ram_size, MAIR_IDX_NORMAL, PERM_RWX);
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/*
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* Remap m1n1 executable code as RX.
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@ -376,25 +355,25 @@ static void mmu_add_default_mappings(void)
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}
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/*
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* Create mapping for 16GB RAM from 0x88_0000_0000 to 0x8c_0000_0000,
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* Create mapping for RAM from 0x88_0000_0000,
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* read/writable/exec by EL0 (but not executable by EL1)
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* With SPRR enabled, this becomes RX_EL0.
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*/
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mmu_add_mapping(0x0800000000 | REGION_RWX_EL0, 0x0800000000, 0x0400000000, MAIR_IDX_NORMAL,
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mmu_add_mapping(0x0800000000 | REGION_RWX_EL0, 0x0800000000, ram_size, MAIR_IDX_NORMAL,
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PERM_RWX_EL0);
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/*
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* Create mapping for 16GB RAM from 0x98_0000_0000 to 0x9c_0000_0000,
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* Create mapping for RAM from 0x98_0000_0000,
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* read/writable by EL0 (but not executable by EL1)
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* With SPRR enabled, this becomes RW_EL0.
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*/
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mmu_add_mapping(0x0800000000 | REGION_RW_EL0, 0x0800000000, 0x0400000000, MAIR_IDX_NORMAL,
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mmu_add_mapping(0x0800000000 | REGION_RW_EL0, 0x0800000000, ram_size, MAIR_IDX_NORMAL,
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PERM_RW_EL0);
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/*
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* Create mapping for 16GB RAM from 0xa8_0000_0000 to 0xac_0000_0000,
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* Create mapping for RAM from 0xa8_0000_0000,
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* read/executable by EL1
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* This allows executing from dynamic regions in EL1
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*/
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mmu_add_mapping(0x0800000000 | REGION_RX_EL1, 0x0800000000, 0x0400000000, MAIR_IDX_NORMAL,
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mmu_add_mapping(0x0800000000 | REGION_RX_EL1, 0x0800000000, ram_size, MAIR_IDX_NORMAL,
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PERM_RX_EL0);
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/*
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35
src/memory.h
35
src/memory.h
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@ -10,6 +10,40 @@
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#define REGION_RW_EL0 0x9000000000
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#define REGION_RX_EL1 0xa000000000
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/*
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* https://armv8-ref.codingbelief.com/en/chapter_d4/d43_2_armv8_translation_table_level_3_descriptor_formats.html
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* PTE_TYPE:PTE_BLOCK indicates that the page table entry (PTE) points to a physical memory block
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* PTE_TYPE:PTE_TABLE indicates that the PTE points to another PTE
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* PTE_TYPE:PTE_PAGE indicates that the PTE points to a single page
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* PTE_FLAG_ACCESS is required to allow access to the memory region
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* PTE_MAIR_IDX sets the MAIR index to be used for this PTE
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*/
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#define PTE_VALID BIT(0)
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#define PTE_TYPE BIT(1)
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#define PTE_BLOCK 0
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#define PTE_TABLE 1
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#define PTE_PAGE 1
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#define PTE_ACCESS BIT(10)
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#define PTE_MAIR_IDX(i) ((i & 7) << 2)
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#define PTE_PXN BIT(53)
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#define PTE_UXN BIT(54)
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#define PTE_AP_RO BIT(7)
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#define PTE_AP_EL0 BIT(6)
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#define PERM_RO_EL0 PTE_AP_EL0 | PTE_AP_RO | PTE_PXN | PTE_UXN
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#define PERM_RW_EL0 PTE_AP_EL0 | PTE_PXN | PTE_UXN
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#define PERM_RX_EL0 PTE_AP_EL0 | PTE_AP_RO
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#define PERM_RWX_EL0 PTE_AP_EL0
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#define PERM_RO PTE_AP_RO | PTE_PXN | PTE_UXN
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#define PERM_RW PTE_PXN | PTE_UXN
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#define PERM_RX PTE_AP_RO | PTE_UXN
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#define PERM_RWX 0
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#define MAIR_IDX_NORMAL 0
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#define MAIR_IDX_DEVICE_nGnRnE 1
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#define MAIR_IDX_DEVICE_nGnRE 2
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#ifndef __ASSEMBLER__
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#include "utils.h"
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@ -29,6 +63,7 @@ void dcsw_op_all(u64 op_type);
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void mmu_init(void);
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void mmu_init_secondary(int cpu);
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void mmu_shutdown(void);
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void mmu_add_mapping(u64 from, u64 to, size_t size, u8 attribute_index, u64 perms);
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u64 mmu_disable(void);
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void mmu_restore(u64 state);
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