From d76f3a66318f3b6cdd686bc0c4a746aae4b1e38e Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Sat, 19 Feb 2022 13:48:06 +0100 Subject: [PATCH] m1n1.hw.DART: coalesce continuos l2 ptes Signed-off-by: Janne Grunau --- proxyclient/m1n1/hw/dart.py | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/proxyclient/m1n1/hw/dart.py b/proxyclient/m1n1/hw/dart.py index 32868242..130e8e50 100644 --- a/proxyclient/m1n1/hw/dart.py +++ b/proxyclient/m1n1/hw/dart.py @@ -330,22 +330,47 @@ class DART(Reloadable): self.pt_cache = {} def dump_table2(self, base, l1_addr): + + def print_block(base, pte, start, last): + pgcount = last - start + pte.OFFSET -= pgcount + print(" page (%4d): %08x ... %08x -> %016x [%d%d]" % ( + start, base + start*0x4000, base + (start+1)*0x4000, + pte.OFFSET << self.PAGE_BITS, pte.SP_PROT_DIS, pte.VALID)) + if start < last: + print(" ==> (%4d): ... %08x -> %016x size: %08x" % ( + last, base + (last+1)*0x4000, + (pte.OFFSET + pgcount - 1) << self.PAGE_BITS, pgcount << self.PAGE_BITS)) + cached, tbl = self.get_pt(l1_addr) unmapped = False + start = 0 + next_pte = self.ptecls(VALID=0) + for i, pte in enumerate(tbl): pte = self.ptecls(pte) if not pte.VALID: if not unmapped: + if next_pte.VALID: + print_block(base, next_pte, start, i) print(" ...") unmapped = True + next_pte = pte continue unmapped = False - print(" page (%d): %08x ... %08x -> %016x [%d%d]" % ( - i, base + i*0x4000, base + (i+1)*0x4000, - pte.OFFSET << self.PAGE_BITS, pte.SP_PROT_DIS, pte.VALID)) + if int(pte) != int(next_pte): + if next_pte.VALID: + print_block(base, next_pte, start, i) + start = i + + next_pte = pte + next_pte.OFFSET += 1 + + if next_pte.VALID: + print_block(base, next_pte, start, 2048) def dump_table(self, base, l1_addr): cached, tbl = self.get_pt(l1_addr)