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m1n1.hw.dart: update pte BIT(1) annotation

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BIT(1) of a page table entry is "disable sub-page protection".

Signed-off-by: Janne Grunau <j@jannau.net>
This commit is contained in:
Janne Grunau 2021-12-07 19:47:57 +01:00 committed by Hector Martin
parent 486ff9ecee
commit d23e09c2f0
1 changed files with 6 additions and 6 deletions
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12
proxyclient/m1n1/hw/dart.py
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@ -45,14 +45,14 @@ class PTE_T8020(Register64):
SP_START = 63, 52 SP_START = 63, 52
SP_END = 51, 40 SP_END = 51, 40
OFFSET = 39, 14 OFFSET = 39, 14
VALID2 = 1 SP_PROT_DIS = 1
VALID = 0 VALID = 0
class PTE_T6000(Register64): class PTE_T6000(Register64):
SP_START = 63, 52 SP_START = 63, 52
SP_END = 51, 40 SP_END = 51, 40
OFFSET = 39, 10 OFFSET = 39, 10
VALID2 = 1 SP_PROT_DIS = 1
VALID = 0 VALID = 0
class R_CONFIG(Register32): class R_CONFIG(Register32):
@ -198,7 +198,7 @@ class DART(Reloadable):
l2addr = self.u.memalign(self.PAGE_SIZE, self.PAGE_SIZE) l2addr = self.u.memalign(self.PAGE_SIZE, self.PAGE_SIZE)
self.pt_cache[l2addr] = [0] * self.Lx_SIZE self.pt_cache[l2addr] = [0] * self.Lx_SIZE
l1pte = self.ptecls( l1pte = self.ptecls(
OFFSET=l2addr >> self.PAGE_BITS, VALID=1, VALID2=1) OFFSET=l2addr >> self.PAGE_BITS, VALID=1, SP_PROT_DIS=1)
l1[l1idx] = l1pte.value l1[l1idx] = l1pte.value
dirty.add(ttbr.ADDR << 12) dirty.add(ttbr.ADDR << 12)
else: else:
@ -209,7 +209,7 @@ class DART(Reloadable):
l2idx = (page >> self.L2_OFF) & self.IDX_MASK l2idx = (page >> self.L2_OFF) & self.IDX_MASK
self.pt_cache[l2addr][l2idx] = self.ptecls( self.pt_cache[l2addr][l2idx] = self.ptecls(
SP_START=0, SP_END=0xfff, SP_START=0, SP_END=0xfff,
OFFSET=paddr >> self.PAGE_BITS, VALID=1, VALID2=1).value OFFSET=paddr >> self.PAGE_BITS, VALID=1, SP_PROT_DIS=1).value
for page in dirty: for page in dirty:
self.flush_pt(page) self.flush_pt(page)
@ -343,7 +343,7 @@ class DART(Reloadable):
print(" page (%d): %08x ... %08x -> %016x [%d%d]" % ( print(" page (%d): %08x ... %08x -> %016x [%d%d]" % (
i, base + i*0x4000, base + (i+1)*0x4000, i, base + i*0x4000, base + (i+1)*0x4000,
pte.OFFSET << self.PAGE_BITS, pte.VALID2, pte.VALID)) pte.OFFSET << self.PAGE_BITS, pte.SP_PROT_DIS, pte.VALID))
print(hex(pte.value)) print(hex(pte.value))
def dump_table(self, base, l1_addr): def dump_table(self, base, l1_addr):
@ -362,7 +362,7 @@ class DART(Reloadable):
print(" table (%d): %08x ... %08x -> %016x [%d%d]" % ( print(" table (%d): %08x ... %08x -> %016x [%d%d]" % (
i, base + i*0x2000000, base + (i+1)*0x2000000, i, base + i*0x2000000, base + (i+1)*0x2000000,
pte.OFFSET << self.PAGE_BITS, pte.VALID2, pte.VALID)) pte.OFFSET << self.PAGE_BITS, pte.SP_PROT_DIS, pte.VALID))
self.dump_table2(base + i*0x2000000, pte.OFFSET << self.PAGE_BITS) self.dump_table2(base + i*0x2000000, pte.OFFSET << self.PAGE_BITS)
def dump_ttbr(self, idx, ttbr): def dump_ttbr(self, idx, ttbr):