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https://github.com/AsahiLinux/m1n1
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m1n1.hw.dart: Move DART support code here, add IOVA resolver
Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin
parent
d025574e1d
commit
c76489e6dd
2 changed files with 222 additions and 99 deletions
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@ -7,103 +7,7 @@ import struct
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from m1n1.setup import *
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from m1n1 import asm
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class R_ERROR(Register32):
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FLAG = 31
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STREAM = 27, 24
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CODE = 23, 0
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READ_FAULT = 4
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WRITE_FAULT = 3
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NO_PTE = 2
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NO_PMD = 1
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NO_TTBR = 0
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class R_STREAM_COMMAND(Register32):
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INVALIDATE = 20
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BUSY = 2
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class R_TCR(Register32):
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BYPASS_DAPF = 12
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BYPASS_DART = 8
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TRANSLATE_ENABLE = 7
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class R_TTBR(Register32):
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VALID = 31
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ADDR = 30, 0
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class R_REMAP(Register32):
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MAP3 = 31, 24
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MAP2 = 23, 16
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MAP1 = 15, 8
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MAP0 = 7, 0
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class DART(RegMap):
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STREAM_COMMAND = 0x20, R_STREAM_COMMAND
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STREAM_SELECT = 0x34, Register32
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ERROR = 0x40, R_ERROR
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ERROR_ADDR_LO = 0x50, Register32
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ERROR_ADDR_HI = 0x54, Register32
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REMAP = irange(0x80, 4, 4), R_REMAP
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TCR = irange(0x100, 16, 4), R_TCR
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TTBR = (irange(0x200, 16, 16), range(0, 16, 4)), R_TTBR
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def __init__(self, base):
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super().__init__(u, base)
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self.base = base
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def dump_table2(self, base, l1_addr):
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tbl = iface.readmem(l1_addr, 0x4000)
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for i in range(0, len(tbl)//8):
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pte = struct.unpack("<Q",tbl[i*8:i*8+8])[0]
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if not (pte & 0b01):
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#print(" page (%d): %08x ... %08x -> DISABLED" % (i, base + i*0x4000, base + (i+1)*0x4000))
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continue
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print(" page (%d): %08x ... %08x -> %016x [%s]" % (i, base + i*0x4000, base + (i+1)*0x4000, pte&~0b11, bin(pte&0b11)))
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def dump_table(self, base, l1_addr):
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tbl = iface.readmem(l1_addr, 0x4000)
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for i in range(0, len(tbl)//8):
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pte = struct.unpack("<Q",tbl[i*8:i*8+8])[0]
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if not (pte & 0b01):
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#print(" table (%d): %08x ... %08x -> DISABLED" % (i, base + i*0x2000000, base + (i+1)*0x2000000))
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continue
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print(" table (%d): %08x ... %08x -> %016x [%s]" % (i, base + i*0x2000000, base + (i+1)*0x2000000, pte&~0b11, bin(pte&0b11)))
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self.dump_table2(base + i*0x2000000, pte & ~0b11)
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def dump_ttbr(self, idx, ttbr):
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if not ttbr.VALID:
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return
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l1_addr = (ttbr.ADDR) << 12
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print(" TTBR%d: %09x" % (idx, l1_addr))
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self.dump_table(0, l1_addr)
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def dump_device(self, idx):
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tcr = self.TCR[idx].reg
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ttbrs = self.TTBR[idx, :]
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print(f"dev {idx:02x}: TCR={tcr!s} TTBRs = [{', '.join(map(str, ttbrs))}]")
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if tcr.TRANSLATE_ENABLE and tcr.BYPASS_DART:
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print(" mode: INVALID")
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elif tcr.TRANSLATE_ENABLE:
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print(" mode: TRANSLATE")
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for idx, ttbr in enumerate(ttbrs):
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self.dump_ttbr(idx, ttbr.reg)
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elif tcr.BYPASS_DART:
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print(" mode: BYPASS")
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else:
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print(" mode: UNKNOWN")
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def dump_all(self):
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for i in range(16):
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self.dump_device(i)
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from m1n1.hw.dart import DART, DARTRegs
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if len(sys.argv) > 1:
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dart_addr = int(sys.argv[1], 16)
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@ -111,6 +15,6 @@ else:
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dart_addr = 0x231304000
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# disp0 DART
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# note that there's another range just before this one
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disp0 = DART(dart_addr)
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disp0 = DART(iface, DARTRegs(u, dart_addr))
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disp0.dump_all()
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disp0.dump_regs()
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disp0.regs.dump_regs()
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219
proxyclient/m1n1/hw/dart.py
Normal file
219
proxyclient/m1n1/hw/dart.py
Normal file
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@ -0,0 +1,219 @@
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# SPDX-License-Identifier: MIT
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import struct
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from ..utils import *
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__all__ = ["DARTRegs", "DART"]
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class R_ERROR(Register32):
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FLAG = 31
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STREAM = 27, 24
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CODE = 23, 0
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READ_FAULT = 4
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WRITE_FAULT = 3
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NO_PTE = 2
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NO_PMD = 1
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NO_TTBR = 0
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class R_STREAM_COMMAND(Register32):
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INVALIDATE = 20
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BUSY = 2
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class R_TCR(Register32):
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BYPASS_DAPF = 12
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BYPASS_DART = 8
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TRANSLATE_ENABLE = 7
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class R_TTBR(Register32):
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VALID = 31
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ADDR = 30, 0
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class R_REMAP(Register32):
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MAP3 = 31, 24
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MAP2 = 23, 16
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MAP1 = 15, 8
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MAP0 = 7, 0
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class PTE(Register64):
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OFFSET = 36, 14
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VALID = 0
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class DARTRegs(RegMap):
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STREAM_COMMAND = 0x20, R_STREAM_COMMAND
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STREAM_SELECT = 0x34, Register32
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ERROR = 0x40, R_ERROR
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ERROR_ADDR_LO = 0x50, Register32
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ERROR_ADDR_HI = 0x54, Register32
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REMAP = irange(0x80, 4, 4), R_REMAP
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TCR = irange(0x100, 16, 4), R_TCR
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TTBR = (irange(0x200, 16, 16), range(0, 16, 4)), R_TTBR
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class DART(Reloadable):
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PAGE_BITS = 14
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PAGE_SIZE = 1 << PAGE_BITS
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L0_SIZE = 4 # TTBR count
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L0_OFF = 36
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L1_OFF = 25
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L2_OFF = 14
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IDX_BITS = 11
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Lx_SIZE = (1 << IDX_BITS)
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IDX_MASK = Lx_SIZE - 1
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def __init__(self, iface, regs):
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self.iface = iface
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self.regs = regs
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self.pt_cache = {}
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def ioread(self, stream, base, size):
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if size == 0:
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return b""
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ranges = self.iotranslate(stream, base, size)
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iova = base
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data = []
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for addr, size in ranges:
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if addr is None:
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raise Exception(f"Unmapped page at iova {iova:#x}")
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data.append(self.iface.readmem(addr, size))
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iova += size
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return b"".join(data)
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def iotranslate(self, stream, start, size):
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if size == 0:
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return []
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tcr = self.regs.TCR[stream].reg
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if tcr.BYPASS_DART and not tcr.TRANSLATE_ENABLE:
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return [(start, size)]
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if tcr.BYPASS_DART or not tcr.TRANSLATE_ENABLE:
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raise Exception(f"Unknown DART mode {tcr}")
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start_page = align_down(start, self.PAGE_SIZE)
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start_off = start - start_page
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end = start + size
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end_page = align_up(end, self.PAGE_SIZE)
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end_size = end - (end_page - self.PAGE_SIZE)
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pages = []
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for page in range(start_page, end_page, self.PAGE_SIZE):
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l0 = page >> self.L0_OFF
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assert l0 < self.L0_SIZE
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ttbr = self.regs.TTBR[stream, l0].reg
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if not ttbr.VALID:
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pages.append(None)
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continue
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l1 = self.get_pt(ttbr.ADDR << 12)
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l1pte = PTE(l1[(page >> self.L1_OFF) & self.IDX_MASK])
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if not l1pte.VALID:
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pages.append(None)
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continue
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l2 = self.get_pt(l1pte.OFFSET << self.PAGE_BITS)
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l2pte = PTE(l2[(page >> self.L2_OFF) & self.IDX_MASK])
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if not l2pte.VALID:
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pages.append(None)
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continue
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pages.append(l2pte.OFFSET << self.PAGE_BITS)
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ranges = []
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for page in pages:
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if not ranges:
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ranges.append((page, self.PAGE_SIZE))
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continue
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laddr, lsize = ranges[-1]
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if ((page is None and laddr is None) or
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(page is not None and laddr == (page - lsize))):
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ranges[-1] = laddr, lsize + self.PAGE_SIZE
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else:
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ranges.append((page, self.PAGE_SIZE))
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ranges[-1] = (ranges[-1][0], ranges[-1][1] - self.PAGE_SIZE + end_size)
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if start_off:
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ranges[0] = (ranges[0][0] + start_off if ranges[0][0] else None,
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ranges[0][1] - start_off)
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return ranges
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def get_pt(self, addr):
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if addr not in self.pt_cache:
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self.pt_cache[addr] = struct.unpack(f"<{self.Lx_SIZE}Q",
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self.iface.readmem(addr, self.PAGE_SIZE))
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return self.pt_cache[addr]
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def invalidate_cache(self):
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self.pt_cache = {}
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def dump_table2(self, base, l1_addr):
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tbl = self.get_pt(l1_addr)
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unmapped = False
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for i, pte in enumerate(tbl):
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if not (pte & 0b01):
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if not unmapped:
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print(" ...")
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unmapped = True
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continue
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unmapped = False
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print(" page (%d): %08x ... %08x -> %016x [%s]" % (i, base + i*0x4000, base + (i+1)*0x4000, pte&~0b11, bin(pte&0b11)))
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def dump_table(self, base, l1_addr):
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tbl = self.get_pt(l1_addr)
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unmapped = False
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for i, pte in enumerate(tbl):
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if not (pte & 0b01):
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if not unmapped:
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print(" ...")
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unmapped = True
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continue
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unmapped = False
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print(" table (%d): %08x ... %08x -> %016x [%s]" % (i, base + i*0x2000000, base + (i+1)*0x2000000, pte&~0b11, bin(pte&0b11)))
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self.dump_table2(base + i*0x2000000, pte & ~0b11)
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def dump_ttbr(self, idx, ttbr):
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if not ttbr.VALID:
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return
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l1_addr = (ttbr.ADDR) << 12
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print(" TTBR%d: %09x" % (idx, l1_addr))
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self.dump_table(0, l1_addr)
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def dump_device(self, idx):
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tcr = self.regs.TCR[idx].reg
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ttbrs = self.regs.TTBR[idx, :]
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print(f"dev {idx:02x}: TCR={tcr!s} TTBRs = [{', '.join(map(str, ttbrs))}]")
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if tcr.TRANSLATE_ENABLE and tcr.BYPASS_DART:
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print(" mode: INVALID")
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elif tcr.TRANSLATE_ENABLE:
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print(" mode: TRANSLATE")
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for idx, ttbr in enumerate(ttbrs):
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self.dump_ttbr(idx, ttbr.reg)
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elif tcr.BYPASS_DART:
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print(" mode: BYPASS")
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else:
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print(" mode: UNKNOWN")
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def dump_all(self):
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for i in range(16):
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self.dump_device(i)
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