mirror of
https://github.com/AsahiLinux/m1n1
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pcie: Add initial t602x support
Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin
parent
046620d4d5
commit
c2c0ac04aa
1 changed files with 266 additions and 27 deletions
293
src/pcie.c
293
src/pcie.c
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@ -44,10 +44,18 @@
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#define APCIE_PHYIF_CTRL 0x024
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#define APCIE_PHYIF_CTRL_RUN BIT(0)
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/* PHY common registers */
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#define APCIE_PHYCMN_CLK 0x000
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#define APCIE_PHYCMN_CLK_MODE GENMASK(1, 0) /* Guesswork */
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#define APCIE_PHYCMN_CLK_MODE_ON 1
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#define APCIE_PHYCMN_CLK_100MHZ BIT(31)
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/* Port registers */
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#define APCIE_PORT_LINKSTS 0x208
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#define APCIE_PORT_LINKSTS_UP BIT(0)
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#define APCIE_PORT_LINKSTS_BUSY BIT(2)
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#define APCIE_PORT_LINKSTS_L2 BIT(6)
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#define APCIE_PORT_APPCLK 0x800
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#define APCIE_PORT_APPCLK_EN BIT(0)
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@ -58,10 +66,14 @@
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#define APCIE_PORT_RESET 0x814
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#define APCIE_PORT_RESET_DIS BIT(0)
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#define APCIE_T602X_PORT_RESET 0x82c
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#define APCIE_T602X_PORT_MSIMAP 0x3800
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/* PCIe capability registers */
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#define PCIE_CAP_BASE 0x70
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#define PCIE_LNKCAP 0x0c
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#define PCIE_LNKCAP_SLS GENMASK(3, 0)
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#define PCIE_LNKCAP_MLW GENMASK(9, 4)
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#define PCIE_LNKCAP2 0x2c
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#define PCIE_LNKCAP2_SLS GENMASK(6, 1)
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#define PCIE_LNKCTL2 0x30
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@ -72,7 +84,18 @@
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#define DWC_DBI_RO_WR 0x8bc
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#define DWC_DBI_RO_WR_EN BIT(0)
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#define DWC_DBI_PORT_LINK_CONTROL 0x710
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#define DWC_DBI_PORT_LINK_DLL_LINK_EN BIT(5)
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#define DWC_DBI_PORT_LINK_FAST_LINK_MODE BIT(7)
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#define DWC_DBI_PORT_LINK_MODE GENMASK(21, 16)
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#define DWC_DBI_PORT_LINK_MODE_1_LANE 0x1
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#define DWC_DBI_PORT_LINK_MODE_2_LANES 0x3
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#define DWC_DBI_PORT_LINK_MODE_4_LANES 0x7
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#define DWC_DBI_PORT_LINK_MODE_8_LANES 0xf
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#define DWC_DBI_PORT_LINK_MODE_16_LANES 0x1f
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#define DWC_DBI_LINK_WIDTH_SPEED_CONTROL 0x80c
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#define DWC_DBI_LINK_WIDTH GENMASK(12, 8)
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#define DWC_DBI_SPEED_CHANGE BIT(17)
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struct fuse_bits {
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@ -107,15 +130,61 @@ const struct fuse_bits pcie_fuse_bits_t8112[] = {
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};
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/* clang-format on */
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enum apcie_type {
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APCIE_T81XX = 0,
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APCIE_T602X = 1,
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};
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struct reg_info {
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enum apcie_type type;
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int shared_reg_count;
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int config_idx;
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int rc_idx;
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int phy_common_idx;
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int phy_idx;
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int phy_ip_idx;
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int axi_idx;
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int fuse_idx;
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bool alt_phy_start;
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};
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static const struct reg_info regs_t8xxx_t600x = {
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.type = APCIE_T81XX,
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.shared_reg_count = 6,
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.config_idx = 0,
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.rc_idx = 1,
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.phy_common_idx = -1,
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.phy_idx = 2,
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.phy_ip_idx = 3,
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.axi_idx = 4,
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.fuse_idx = 5,
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};
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static const struct reg_info regs_t602x = {
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.type = APCIE_T602X,
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.shared_reg_count = 8,
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.config_idx = 0,
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.rc_idx = 1,
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// 2 = phy unknown?
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.phy_common_idx = 3,
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.phy_idx = 4,
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.phy_ip_idx = 5,
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.axi_idx = 6,
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.fuse_idx = 7,
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};
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static bool pcie_initialized = false;
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static u64 rc_base;
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static u64 phy_common_base;
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static u64 phy_base;
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static u64 phy_ip_base;
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static u64 fuse_base;
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static u32 port_count;
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static u64 port_base[8];
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#define SHARED_REG_COUNT 6
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static u64 port_ltssm_base[8];
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static u64 port_phy_base[8];
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static u64 port_intr2axi_base[8];
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static const struct reg_info *pcie_regs;
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int pcie_init(void)
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{
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@ -135,13 +204,20 @@ int pcie_init(void)
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if (adt_is_compatible(adt, adt_offset, "apcie,t8103")) {
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fuse_bits = pcie_fuse_bits_t8103;
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pcie_regs = ®s_t8xxx_t600x;
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printf("pcie: Initializing t8103 PCIe controller\n");
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} else if (adt_is_compatible(adt, adt_offset, "apcie,t6000")) {
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fuse_bits = pcie_fuse_bits_t6000;
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pcie_regs = ®s_t8xxx_t600x;
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printf("pcie: Initializing t6000 PCIe controller\n");
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} else if (adt_is_compatible(adt, adt_offset, "apcie,t8112")) {
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fuse_bits = pcie_fuse_bits_t8112;
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pcie_regs = ®s_t8xxx_t600x;
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printf("pcie: Initializing t8112 PCIe controller\n");
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} else if (adt_is_compatible(adt, adt_offset, "apcie,t6020")) {
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fuse_bits = NULL;
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pcie_regs = ®s_t602x;
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printf("pcie: Initializing t6020 PCIe controller\n");
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} else {
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printf("pcie: Unsupported compatible\n");
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return -1;
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@ -153,28 +229,37 @@ int pcie_init(void)
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}
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u64 config_base;
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if (adt_get_reg(adt, adt_path, "reg", 0, &config_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", 0, path);
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if (adt_get_reg(adt, adt_path, "reg", pcie_regs->config_idx, &config_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", pcie_regs->config_idx, path);
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return -1;
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}
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if (adt_get_reg(adt, adt_path, "reg", 1, &rc_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", 1, path);
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if (adt_get_reg(adt, adt_path, "reg", pcie_regs->rc_idx, &rc_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", pcie_regs->rc_idx, path);
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return -1;
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}
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if (adt_get_reg(adt, adt_path, "reg", 2, &phy_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", 2, path);
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if (pcie_regs->phy_common_idx != -1) {
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if (adt_get_reg(adt, adt_path, "reg", pcie_regs->phy_common_idx, &phy_common_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", pcie_regs->phy_idx, path);
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return -1;
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}
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} else {
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phy_common_base = 0;
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}
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if (adt_get_reg(adt, adt_path, "reg", pcie_regs->phy_idx, &phy_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", pcie_regs->phy_idx, path);
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return -1;
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}
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if (adt_get_reg(adt, adt_path, "reg", 3, &phy_ip_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", 3, path);
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if (adt_get_reg(adt, adt_path, "reg", pcie_regs->phy_ip_idx, &phy_ip_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", pcie_regs->phy_ip_idx, path);
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return -1;
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}
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if (adt_get_reg(adt, adt_path, "reg", 5, &fuse_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", 5, path);
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if (adt_get_reg(adt, adt_path, "reg", pcie_regs->fuse_idx, &fuse_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", pcie_regs->fuse_idx, path);
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return -1;
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}
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@ -184,7 +269,7 @@ int pcie_init(void)
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return -1;
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}
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int port_regs = (reg_len / 16) - SHARED_REG_COUNT;
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int port_regs = (reg_len / 16) - pcie_regs->shared_reg_count;
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if (port_regs % port_count) {
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printf("pcie: %d port registers do not evenly divide into %d ports\n", port_regs,
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@ -200,7 +285,7 @@ int pcie_init(void)
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return -1;
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}
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if (tunables_apply_local(path, "apcie-axi2af-tunables", 4)) {
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if (tunables_apply_local(path, "apcie-axi2af-tunables", pcie_regs->axi_idx)) {
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printf("pcie: Error applying %s for %s\n", "apcie-axi2af-tunables", path);
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return -1;
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}
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@ -208,7 +293,9 @@ int pcie_init(void)
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/* ??? */
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write32(rc_base + 0x4, 0);
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if (tunables_apply_local(path, "apcie-common-tunables", 1)) {
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if (!adt_getprop(adt, adt_offset, "apcie-common-tunables", NULL)) {
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printf("pcie: No common tunables\n");
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} else if (tunables_apply_local(path, "apcie-common-tunables", pcie_regs->rc_idx)) {
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printf("pcie: Error applying %s for %s\n", "apcie-common-tunables", path);
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return -1;
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}
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@ -217,11 +304,21 @@ int pcie_init(void)
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* Initialize PHY.
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*/
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if (tunables_apply_local(path, "apcie-phy-tunables", 2)) {
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if (!adt_getprop(adt, adt_offset, "apcie-phy-tunables", NULL)) {
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printf("pcie: No PHY tunables\n");
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} else if (tunables_apply_local(path, "apcie-phy-tunables", pcie_regs->phy_idx)) {
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printf("pcie: Error applying %s for %s\n", "apcie-phy-tunables", path);
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return -1;
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}
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if (pcie_regs->type == APCIE_T602X) {
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if (poll32(phy_common_base + APCIE_PHYCMN_CLK, APCIE_PHYCMN_CLK_100MHZ,
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APCIE_PHYCMN_CLK_100MHZ, 250000)) {
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printf("pcie: Reference clock not available\n");
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return -1;
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}
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}
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set32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0REQ);
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if (poll32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0ACK, APCIE_PHY_CTRL_CLK0ACK, 50000)) {
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printf("pcie: Timeout enabling PHY CLK0\n");
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@ -238,11 +335,15 @@ int pcie_init(void)
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udelay(1);
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/* ??? */
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set32(rc_base + APCIE_PHYIF_CTRL, APCIE_PHYIF_CTRL_RUN);
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udelay(1);
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if (pcie_regs->type == APCIE_T81XX) {
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set32(rc_base + APCIE_PHYIF_CTRL, APCIE_PHYIF_CTRL_RUN);
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udelay(1);
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} else if (pcie_regs->type == APCIE_T602X) {
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set32(phy_base + 4, 0x01);
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}
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/* Apply "fuses". */
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for (int i = 0; fuse_bits[i].width; i++) {
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for (int i = 0; fuse_bits && fuse_bits[i].width; i++) {
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u32 fuse;
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fuse = (read32(fuse_base + fuse_bits[i].src_reg) >> fuse_bits[i].src_bit);
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fuse &= (1 << fuse_bits[i].width) - 1;
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@ -251,15 +352,34 @@ int pcie_init(void)
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fuse << fuse_bits[i].tgt_bit);
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}
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if (tunables_apply_local(path, "apcie-phy-ip-pll-tunables", 3)) {
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if (tunables_apply_local(path, "apcie-phy-ip-pll-tunables", pcie_regs->phy_ip_idx)) {
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printf("pcie: Error applying %s for %s\n", "apcie-phy-ip-pll-tunables", path);
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return -1;
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}
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if (tunables_apply_local(path, "apcie-phy-ip-auspma-tunables", 3)) {
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if (tunables_apply_local(path, "apcie-phy-ip-auspma-tunables", pcie_regs->phy_ip_idx)) {
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printf("pcie: Error applying %s for %s\n", "apcie-phy-ip-auspma-tunables", path);
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return -1;
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}
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if (pcie_regs->type == APCIE_T602X) {
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set32(phy_base + 4, 0x10);
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mask32(phy_common_base + APCIE_PHYCMN_CLK, APCIE_PHYCMN_CLK_MODE,
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FIELD_PREP(APCIE_PHYCMN_CLK_MODE, 1));
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if (poll32(phy_base + 0x8, 1, 1, 250000)) {
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printf("pcie: PHY clock enable timed out\n");
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return -1;
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}
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set32(phy_base + APCIE_PHY_CTRL, 0x300);
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write32(rc_base + 0x54, 0x140);
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write32(rc_base + 0x50, 0x1);
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if (poll32(rc_base + 0x58, 1, 1, 250000)) {
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printf("pcie: Failed to initialize RC thing\n");
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return -1;
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}
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clear32(rc_base + 0x3c, 0x1);
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pmgr_adt_power_disable_index(path, 1);
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}
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for (u32 port = 0; port < port_count; port++) {
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char bridge[64];
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int bridge_offset;
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@ -275,13 +395,67 @@ int pcie_init(void)
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printf("pcie: Initializing port %d\n", port);
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if (adt_get_reg(adt, adt_path, "reg", port * port_reg_cnt + SHARED_REG_COUNT,
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if (adt_get_reg(adt, adt_path, "reg", port * port_reg_cnt + pcie_regs->shared_reg_count,
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&port_base[port], NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n",
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port * port_reg_cnt + SHARED_REG_COUNT, path);
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port * port_reg_cnt + pcie_regs->shared_reg_count, path);
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return -1;
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}
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if (adt_get_reg(adt, adt_path, "reg", port * port_reg_cnt + pcie_regs->shared_reg_count + 1,
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&port_ltssm_base[port], NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n",
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port * port_reg_cnt + pcie_regs->shared_reg_count + 1, path);
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return -1;
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}
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if (adt_get_reg(adt, adt_path, "reg", port * port_reg_cnt + pcie_regs->shared_reg_count + 2,
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&port_phy_base[port], NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n",
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port * port_reg_cnt + pcie_regs->shared_reg_count + 2, path);
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return -1;
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}
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if (port_reg_cnt >= 5) {
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if (adt_get_reg(adt, adt_path, "reg",
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port * port_reg_cnt + pcie_regs->shared_reg_count + 4,
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&port_intr2axi_base[port], NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n",
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port * port_reg_cnt + pcie_regs->shared_reg_count + 4, path);
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return -1;
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}
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} else {
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port_intr2axi_base[port] = 0;
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}
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if (pcie_regs->type == APCIE_T602X) {
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set32(rc_base + 0x3c, 0x1);
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// ??????
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write32(port_base[port] + 0x10, 0x2);
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write32(port_base[port] + 0x88, 0x110);
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write32(port_base[port] + 0x100, 0xffffffff);
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write32(port_base[port] + 0x148, 0xffffffff);
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write32(port_base[port] + 0x210, 0xffffffff);
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write32(port_base[port] + 0x80, 0x0);
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write32(port_base[port] + 0x84, 0x0);
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write32(port_base[port] + 0x104, 0x7fffffff);
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write32(port_base[port] + 0x124, 0x100);
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write32(port_base[port] + 0x16c, 0x0);
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write32(port_base[port] + 0x13c, 0x10);
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write32(port_base[port] + 0x800, 0x100100);
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write32(port_base[port] + 0x808, 0x1000ff);
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write32(port_base[port] + 0x82c, 0x0);
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for (int i = 0; i < 512; i++)
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write32(port_base[port] + APCIE_T602X_PORT_MSIMAP + 4 * i, 0);
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write32(port_base[port] + 0x397c, 0x0);
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write32(port_base[port] + 0x130, 0x3000000);
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write32(port_base[port] + 0x140, 0x10);
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write32(port_base[port] + 0x144, 0x253770);
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write32(port_base[port] + 0x21c, 0x0);
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write32(port_base[port] + 0x834, 0x0);
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}
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if (tunables_apply_local_addr(bridge, "apcie-config-tunables", port_base[port])) {
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printf("pcie: Error applying %s for %s\n", "apcie-config-tunables", bridge);
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return -1;
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@ -289,8 +463,33 @@ int pcie_init(void)
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set32(port_base[port] + APCIE_PORT_APPCLK, APCIE_PORT_APPCLK_EN);
|
||||
|
||||
/* PERSTN */
|
||||
set32(port_base[port] + APCIE_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
if (pcie_regs->type == APCIE_T602X) {
|
||||
clear32(port_phy_base[port] + APCIE_PHY_CTRL,
|
||||
APCIE_PHY_CTRL_CLK0REQ | APCIE_PHY_CTRL_CLK1REQ);
|
||||
|
||||
set32(port_phy_base[port] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0REQ);
|
||||
if (poll32(port_phy_base[port] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0ACK,
|
||||
APCIE_PHY_CTRL_CLK0ACK, 50000)) {
|
||||
printf("pcie: Timeout enabling PHY CLK0\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
set32(port_phy_base[port] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK1REQ);
|
||||
if (poll32(port_phy_base[port] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK1ACK,
|
||||
APCIE_PHY_CTRL_CLK1ACK, 50000)) {
|
||||
printf("pcie: Timeout enabling PHY CLK1\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
clear32(port_phy_base[port] + APCIE_PHY_CTRL, 0x4000);
|
||||
set32(port_phy_base[port] + APCIE_PHY_CTRL, 0x200);
|
||||
set32(port_phy_base[port] + APCIE_PHY_CTRL, 0x400);
|
||||
|
||||
set32(port_base[port] + APCIE_T602X_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
} else {
|
||||
/* PERSTN */
|
||||
set32(port_base[port] + APCIE_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
}
|
||||
|
||||
if (poll32(port_base[port] + APCIE_PORT_STATUS, APCIE_PORT_STATUS_RUN,
|
||||
APCIE_PORT_STATUS_RUN, 250000)) {
|
||||
|
|
@ -303,6 +502,24 @@ int pcie_init(void)
|
|||
return -1;
|
||||
}
|
||||
|
||||
/* Do it again? */
|
||||
if (pcie_regs->type == APCIE_T602X) {
|
||||
clear32(port_base[port] + APCIE_T602X_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
set32(port_base[port] + APCIE_T602X_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
|
||||
if (poll32(port_base[port] + APCIE_PORT_LINKSTS, APCIE_PORT_LINKSTS_BUSY, 0, 250000)) {
|
||||
printf("pcie: Port failed to become idle on %s\n", bridge);
|
||||
return -1;
|
||||
}
|
||||
|
||||
udelay(1000);
|
||||
|
||||
write32(port_ltssm_base[port] + 0x10, 0x2);
|
||||
write32(port_ltssm_base[port] + 0x1c, 0x4);
|
||||
set32(port_ltssm_base[port] + 0x20, 0x2);
|
||||
write32(port_ltssm_base[port] + 0x14, 0x1);
|
||||
}
|
||||
|
||||
/* Make Designware PCIe Core registers writable. */
|
||||
set32(config_base + DWC_DBI_RO_WR, DWC_DBI_RO_WR_EN);
|
||||
|
||||
|
|
@ -356,13 +573,32 @@ int pcie_init(void)
|
|||
|
||||
mask16(config_base + PCIE_CAP_BASE + PCIE_LNKCTL2, PCIE_LNKCTL2_TLS,
|
||||
FIELD_PREP(PCIE_LNKCTL2_TLS, max_speed));
|
||||
|
||||
set32(config_base + DWC_DBI_LINK_WIDTH_SPEED_CONTROL, DWC_DBI_SPEED_CHANGE);
|
||||
}
|
||||
|
||||
set32(config_base + DWC_DBI_LINK_WIDTH_SPEED_CONTROL, DWC_DBI_SPEED_CHANGE);
|
||||
/* Max link width 1 */
|
||||
mask32(config_base + DWC_DBI_PORT_LINK_CONTROL, DWC_DBI_PORT_LINK_MODE,
|
||||
FIELD_PREP(DWC_DBI_PORT_LINK_MODE, DWC_DBI_PORT_LINK_MODE_1_LANE));
|
||||
mask32(config_base + DWC_DBI_LINK_WIDTH_SPEED_CONTROL, DWC_DBI_LINK_WIDTH,
|
||||
FIELD_PREP(DWC_DBI_LINK_WIDTH, 1));
|
||||
mask32(config_base + PCIE_CAP_BASE + PCIE_LNKCAP, PCIE_LNKCAP_MLW,
|
||||
FIELD_PREP(PCIE_LNKCAP_MLW, 1));
|
||||
|
||||
/* Make Designware PCIe Core registers readonly. */
|
||||
clear32(config_base + DWC_DBI_RO_WR, DWC_DBI_RO_WR_EN);
|
||||
|
||||
if (pcie_regs->type == APCIE_T602X) {
|
||||
write32(port_base[port] + 0x4020, 0x3);
|
||||
write32(port_intr2axi_base[port] + 0x80, 0x1);
|
||||
|
||||
clear32(rc_base + 0x3c, 0x1);
|
||||
for (int i = 0; i < 32; i++)
|
||||
write32(port_base[port] + APCIE_T602X_PORT_MSIMAP + 4 * i, 0x80000000 | i);
|
||||
}
|
||||
|
||||
read32(port_base[port] + APCIE_PORT_LINKSTS);
|
||||
|
||||
/* Move to the next PCIe device on this bus. */
|
||||
config_base += (1 << 15);
|
||||
}
|
||||
|
|
@ -379,7 +615,10 @@ int pcie_shutdown(void)
|
|||
return 0;
|
||||
|
||||
for (u32 port = 0; port < port_count; port++) {
|
||||
clear32(port_base[port] + APCIE_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
if (pcie_regs->type == APCIE_T602X)
|
||||
clear32(port_base[port] + APCIE_T602X_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
else
|
||||
clear32(port_base[port] + APCIE_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
clear32(port_base[port] + APCIE_PORT_APPCLK, APCIE_PORT_APPCLK_EN);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue