From c1f14a4738b6d4106240c9284f4a900116c1206c Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Wed, 1 Feb 2023 14:08:35 +0100 Subject: [PATCH] dcp: add dptx-phy support for j473/t8112 Phy "implementation" is just a replay of a macos trace with an 1920x1080 display. --- Makefile | 2 +- src/dcp/dp_phy.h | 12 + src/dcp/dptx_phy.c | 529 +++++++++++++++++++++++++++++++++++++++++++++ src/dcp/dptxep.c | 10 +- src/dcp/dptxep.h | 4 +- src/display.c | 4 +- 6 files changed, 557 insertions(+), 4 deletions(-) create mode 100644 src/dcp/dp_phy.h create mode 100644 src/dcp/dptx_phy.c diff --git a/Makefile b/Makefile index 982cea69..4d5549c7 100644 --- a/Makefile +++ b/Makefile @@ -74,7 +74,7 @@ LIBFDT_OBJECTS := $(patsubst %,libfdt/%, \ fdt_wip.o fdt.o) DCP_OBJECTS := $(patsubst %,dcp/%, \ - dptxep.o parser.o) + dptx_phy.o dptxep.o parser.o) OBJECTS := \ adt.o \ diff --git a/src/dcp/dp_phy.h b/src/dcp/dp_phy.h new file mode 100644 index 00000000..81f944e6 --- /dev/null +++ b/src/dcp/dp_phy.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ + +#ifndef DCP_DP_PHY_H +#define DCP_DP_PHY_H + +typedef struct dptx_phy dptx_phy_t; + +int dptx_phy_configure(dptx_phy_t *phy, int state); +dptx_phy_t *dptx_phy_init(const char *phy_path); +void dptx_phy_shutdown(dptx_phy_t *phy); + +#endif /* DCP_DP_PHY_H */ diff --git a/src/dcp/dptx_phy.c b/src/dcp/dptx_phy.c new file mode 100644 index 00000000..b8d1e39c --- /dev/null +++ b/src/dcp/dptx_phy.c @@ -0,0 +1,529 @@ +/* SPDX-License-Identifier: MIT */ + +#include "dp_phy.h" +#include "dptxep.h" +#include "malloc.h" + +#include "../adt.h" +#include "../utils.h" + +typedef struct dptx_phy { + u64 regs[2]; +} dptx_phy_t; + +static int dptx_phy_activate(dptx_phy_t *phy) +{ +#if 1 + // MMIO: R.4 0x23c500010 (dptx-phy[1], offset 0x10) = 0x0 + read32(phy->regs[1] + 0x10); + // MMIO: W.4 0x23c500010 (dptx-phy[1], offset 0x10) = 0x0 + write32(phy->regs[1] + 0x10, 0x0); + // MMIO: R.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x444 + read32(phy->regs[1] + 0x48); + // MMIO: W.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x454 + write32(phy->regs[1] + 0x48, 0x454); + // MMIO: R.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x454 + read32(phy->regs[1] + 0x48); + // MMIO: W.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x474 + write32(phy->regs[1] + 0x48, 0x474); + // MMIO: R.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x474 + read32(phy->regs[1] + 0x48); + // MMIO: W.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x434 + write32(phy->regs[1] + 0x48, 0x434); + // MMIO: R.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x434 + read32(phy->regs[1] + 0x48); + // MMIO: W.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x534 + write32(phy->regs[1] + 0x48, 0x534); + // MMIO: R.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x534 + read32(phy->regs[1] + 0x48); + // MMIO: W.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x734 + write32(phy->regs[1] + 0x48, 0x734); + // MMIO: R.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x734 + read32(phy->regs[1] + 0x48); + // MMIO: W.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x334 + write32(phy->regs[1] + 0x48, 0x334); + // MMIO: R.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x334 + read32(phy->regs[1] + 0x48); + // MMIO: W.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x335 + write32(phy->regs[1] + 0x48, 0x335); + // MMIO: R.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x335 + read32(phy->regs[1] + 0x48); + // MMIO: W.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x337 + write32(phy->regs[1] + 0x48, 0x337); + // MMIO: R.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x337 + read32(phy->regs[1] + 0x48); + // MMIO: W.4 0x23c500048 (dptx-phy[1], offset 0x48) = 0x333 + write32(phy->regs[1] + 0x48, 0x333); + // MMIO: R.4 0x23c542014 (dptx-phy[0], offset 0x2014) = 0x80a0c + read32(phy->regs[0] + 0x2014); + // MMIO: W.4 0x23c542014 (dptx-phy[0], offset 0x2014) = 0x300a0c + write32(phy->regs[0] + 0x2014, 0x300a0c); + // MMIO: R.4 0x23c5420b8 (dptx-phy[0], offset 0x20b8) = 0x644800 + read32(phy->regs[0] + 0x20b8); + // MMIO: W.4 0x23c5420b8 (dptx-phy[0], offset 0x20b8) = 0x654800 + write32(phy->regs[0] + 0x20b8, 0x654800); + // MMIO: R.4 0x23c542220 (dptx-phy[0], offset 0x2220) = 0x11090a2 + read32(phy->regs[0] + 0x2220); + // MMIO: W.4 0x23c542220 (dptx-phy[0], offset 0x2220) = 0x11090a0 + write32(phy->regs[0] + 0x2220, 0x11090a0); + // MMIO: R.4 0x23c54222c (dptx-phy[0], offset 0x222c) = 0x103003 + read32(phy->regs[0] + 0x222c); + // MMIO: W.4 0x23c54222c (dptx-phy[0], offset 0x222c) = 0x103803 + write32(phy->regs[0] + 0x222c, 0x103803); + // MMIO: R.4 0x23c54222c (dptx-phy[0], offset 0x222c) = 0x103803 + read32(phy->regs[0] + 0x222c); + // MMIO: W.4 0x23c54222c (dptx-phy[0], offset 0x222c) = 0x103903 + write32(phy->regs[0] + 0x222c, 0x103903); + // MMIO: R.4 0x23c542230 (dptx-phy[0], offset 0x2230) = 0x2308804 + read32(phy->regs[0] + 0x2230); + // MMIO: W.4 0x23c542230 (dptx-phy[0], offset 0x2230) = 0x2208804 + write32(phy->regs[0] + 0x2230, 0x2208804); + // MMIO: R.4 0x23c542278 (dptx-phy[0], offset 0x2278) = 0x18300811 + read32(phy->regs[0] + 0x2278); + // MMIO: W.4 0x23c542278 (dptx-phy[0], offset 0x2278) = 0x10300811 + write32(phy->regs[0] + 0x2278, 0x10300811); + // MMIO: R.4 0x23c5422a4 (dptx-phy[0], offset 0x22a4) = 0x1044200 + read32(phy->regs[0] + 0x22a4); + // MMIO: W.4 0x23c5422a4 (dptx-phy[0], offset 0x22a4) = 0x1044201 + write32(phy->regs[0] + 0x22a4, 0x1044201); + // MMIO: R.4 0x23c544008 (dptx-phy[0], offset 0x4008) = 0x18030 + read32(phy->regs[0] + 0x4008); + // MMIO: W.4 0x23c544008 (dptx-phy[0], offset 0x4008) = 0x30030 + write32(phy->regs[0] + 0x4008, 0x30030); + // MMIO: R.4 0x23c544008 (dptx-phy[0], offset 0x4008) = 0x30030 + read32(phy->regs[0] + 0x4008); + // MMIO: W.4 0x23c544008 (dptx-phy[0], offset 0x4008) = 0x30010 + write32(phy->regs[0] + 0x4008, 0x30010); + // MMIO: R.4 0x23c54420c (dptx-phy[0], offset 0x420c) = 0x88e3 + read32(phy->regs[0] + 0x420c); + // MMIO: W.4 0x23c54420c (dptx-phy[0], offset 0x420c) = 0x88c3 + write32(phy->regs[0] + 0x420c, 0x88c3); + // MMIO: R.4 0x23c544600 (dptx-phy[0], offset 0x4600) = 0x0 + read32(phy->regs[0] + 0x4600); + // MMIO: W.4 0x23c544600 (dptx-phy[0], offset 0x4600) = 0x8000000 + write32(phy->regs[0] + 0x4600, 0x8000000); + // MMIO: R.4 0x23c545040 (dptx-phy[0], offset 0x5040) = 0x21780 + read32(phy->regs[0] + 0x5040); + // MMIO: W.4 0x23c545040 (dptx-phy[0], offset 0x5040) = 0x221780 + write32(phy->regs[0] + 0x5040, 0x221780); + // MMIO: R.4 0x23c546040 (dptx-phy[0], offset 0x6040) = 0x21780 + read32(phy->regs[0] + 0x6040); + // MMIO: W.4 0x23c546040 (dptx-phy[0], offset 0x6040) = 0x221780 + write32(phy->regs[0] + 0x6040, 0x221780); + // MMIO: R.4 0x23c547040 (dptx-phy[0], offset 0x7040) = 0x21780 + read32(phy->regs[0] + 0x7040); + // MMIO: W.4 0x23c547040 (dptx-phy[0], offset 0x7040) = 0x221780 + write32(phy->regs[0] + 0x7040, 0x221780); + // MMIO: R.4 0x23c548040 (dptx-phy[0], offset 0x8040) = 0x21780 + read32(phy->regs[0] + 0x8040); + // MMIO: W.4 0x23c548040 (dptx-phy[0], offset 0x8040) = 0x221780 + write32(phy->regs[0] + 0x8040, 0x221780); + // MMIO: R.4 0x23c545040 (dptx-phy[0], offset 0x5040) = 0x221780 + read32(phy->regs[0] + 0x5040); + // MMIO: W.4 0x23c545040 (dptx-phy[0], offset 0x5040) = 0x2a1780 + write32(phy->regs[0] + 0x5040, 0x2a1780); + // MMIO: R.4 0x23c546040 (dptx-phy[0], offset 0x6040) = 0x221780 + read32(phy->regs[0] + 0x6040); + // MMIO: W.4 0x23c546040 (dptx-phy[0], offset 0x6040) = 0x2a1780 + write32(phy->regs[0] + 0x6040, 0x2a1780); + // MMIO: R.4 0x23c547040 (dptx-phy[0], offset 0x7040) = 0x221780 + read32(phy->regs[0] + 0x7040); + // MMIO: W.4 0x23c547040 (dptx-phy[0], offset 0x7040) = 0x2a1780 + write32(phy->regs[0] + 0x7040, 0x2a1780); + // MMIO: R.4 0x23c548040 (dptx-phy[0], offset 0x8040) = 0x221780 + read32(phy->regs[0] + 0x8040); + // MMIO: W.4 0x23c548040 (dptx-phy[0], offset 0x8040) = 0x2a1780 + write32(phy->regs[0] + 0x8040, 0x2a1780); + // MMIO: R.4 0x23c545244 (dptx-phy[0], offset 0x5244) = 0x18 + read32(phy->regs[0] + 0x5244); + // MMIO: W.4 0x23c545244 (dptx-phy[0], offset 0x5244) = 0x8 + write32(phy->regs[0] + 0x5244, 0x8); + // MMIO: R.4 0x23c546244 (dptx-phy[0], offset 0x6244) = 0x18 + read32(phy->regs[0] + 0x6244); + // MMIO: W.4 0x23c546244 (dptx-phy[0], offset 0x6244) = 0x8 + write32(phy->regs[0] + 0x6244, 0x8); + // MMIO: R.4 0x23c547244 (dptx-phy[0], offset 0x7244) = 0x18 + read32(phy->regs[0] + 0x7244); + // MMIO: W.4 0x23c547244 (dptx-phy[0], offset 0x7244) = 0x8 + write32(phy->regs[0] + 0x7244, 0x8); + // MMIO: R.4 0x23c548244 (dptx-phy[0], offset 0x8244) = 0x18 + read32(phy->regs[0] + 0x8244); + // MMIO: W.4 0x23c548244 (dptx-phy[0], offset 0x8244) = 0x8 + write32(phy->regs[0] + 0x8244, 0x8); + // MMIO: R.4 0x23c542214 (dptx-phy[0], offset 0x2214) = 0x1e0 + read32(phy->regs[0] + 0x2214); + // MMIO: W.4 0x23c542214 (dptx-phy[0], offset 0x2214) = 0x1e1 + write32(phy->regs[0] + 0x2214, 0x1e1); + // MMIO: R.4 0x23c542224 (dptx-phy[0], offset 0x2224) = 0x20086001 + read32(phy->regs[0] + 0x2224); + // MMIO: W.4 0x23c542224 (dptx-phy[0], offset 0x2224) = 0x20086000 + write32(phy->regs[0] + 0x2224, 0x20086000); + // MMIO: R.4 0x23c542200 (dptx-phy[0], offset 0x2200) = 0x2000 + read32(phy->regs[0] + 0x2200); + // MMIO: W.4 0x23c542200 (dptx-phy[0], offset 0x2200) = 0x2002 + write32(phy->regs[0] + 0x2200, 0x2002); + // MMIO: R.4 0x23c541000 (dptx-phy[0], offset 0x1000) = 0xe0000003 + read32(phy->regs[0] + 0x1000); + // MMIO: W.4 0x23c541000 (dptx-phy[0], offset 0x1000) = 0xe0000001 + write32(phy->regs[0] + 0x1000, 0xe0000001); + // MMIO: R.4 0x23c544004 (dptx-phy[0], offset 0x4004) = 0x41 + read32(phy->regs[0] + 0x4004); + // MMIO: W.4 0x23c544004 (dptx-phy[0], offset 0x4004) = 0x49 + write32(phy->regs[0] + 0x4004, 0x49); + // MMIO: R.4 0x23c544404 (dptx-phy[0], offset 0x4404) = 0x555d444 + read32(phy->regs[0] + 0x4404); + // MMIO: W.4 0x23c544404 (dptx-phy[0], offset 0x4404) = 0x555d444 + write32(phy->regs[0] + 0x4404, 0x555d444); + // MMIO: R.4 0x23c544404 (dptx-phy[0], offset 0x4404) = 0x555d444 + read32(phy->regs[0] + 0x4404); + // MMIO: W.4 0x23c544404 (dptx-phy[0], offset 0x4404) = 0x555d444 + write32(phy->regs[0] + 0x4404, 0x555d444); + // MMIO: R.4 0x23c544000 (dptx-phy[0], offset 0x4000) = 0x41021ac + read32(phy->regs[0] + 0x4000); + // MMIO: W.4 0x23c544000 (dptx-phy[0], offset 0x4000) = 0x41021ac + write32(phy->regs[0] + 0x4000, 0x41021ac); + // MMIO: R.4 0x23c545000 (dptx-phy[0], offset 0x5000) = 0x300 + read32(phy->regs[0] + 0x5000); + // MMIO: W.4 0x23c545000 (dptx-phy[0], offset 0x5000) = 0x300 + write32(phy->regs[0] + 0x5000, 0x300); + // MMIO: R.4 0x23c546000 (dptx-phy[0], offset 0x6000) = 0x300 + read32(phy->regs[0] + 0x6000); + // MMIO: W.4 0x23c546000 (dptx-phy[0], offset 0x6000) = 0x300 + write32(phy->regs[0] + 0x6000, 0x300); + // MMIO: R.4 0x23c547000 (dptx-phy[0], offset 0x7000) = 0x300 + read32(phy->regs[0] + 0x7000); + // MMIO: W.4 0x23c547000 (dptx-phy[0], offset 0x7000) = 0x300 + write32(phy->regs[0] + 0x7000, 0x300); + // MMIO: R.4 0x23c548000 (dptx-phy[0], offset 0x8000) = 0x300 + read32(phy->regs[0] + 0x8000); + // MMIO: W.4 0x23c548000 (dptx-phy[0], offset 0x8000) = 0x300 + write32(phy->regs[0] + 0x8000, 0x300); + // MMIO: R.4 0x23c545000 (dptx-phy[0], offset 0x5000) = 0x300 + read32(phy->regs[0] + 0x5000); + // MMIO: W.4 0x23c545000 (dptx-phy[0], offset 0x5000) = 0x300 + write32(phy->regs[0] + 0x5000, 0x300); + // MMIO: R.4 0x23c546000 (dptx-phy[0], offset 0x6000) = 0x300 + read32(phy->regs[0] + 0x6000); + // MMIO: W.4 0x23c546000 (dptx-phy[0], offset 0x6000) = 0x300 + write32(phy->regs[0] + 0x6000, 0x300); + // MMIO: R.4 0x23c547000 (dptx-phy[0], offset 0x7000) = 0x300 + read32(phy->regs[0] + 0x7000); + // MMIO: W.4 0x23c547000 (dptx-phy[0], offset 0x7000) = 0x300 + write32(phy->regs[0] + 0x7000, 0x300); + // MMIO: R.4 0x23c548000 (dptx-phy[0], offset 0x8000) = 0x300 + read32(phy->regs[0] + 0x8000); + // MMIO: W.4 0x23c548000 (dptx-phy[0], offset 0x8000) = 0x300 + write32(phy->regs[0] + 0x8000, 0x300); + // MMIO: R.4 0x23c544200 (dptx-phy[0], offset 0x4200) = 0x4002430 + read32(phy->regs[0] + 0x4200); + // MMIO: W.4 0x23c544200 (dptx-phy[0], offset 0x4200) = 0x4002420 + write32(phy->regs[0] + 0x4200, 0x4002420); + // MMIO: R.4 0x23c544600 (dptx-phy[0], offset 0x4600) = 0x8000000 + read32(phy->regs[0] + 0x4600); + // MMIO: W.4 0x23c544600 (dptx-phy[0], offset 0x4600) = 0x8000000 + write32(phy->regs[0] + 0x4600, 0x8000000); + // MMIO: R.4 0x23c544600 (dptx-phy[0], offset 0x4600) = 0x8000000 + read32(phy->regs[0] + 0x4600); + // MMIO: W.4 0x23c544600 (dptx-phy[0], offset 0x4600) = 0x8000001 + write32(phy->regs[0] + 0x4600, 0x8000001); + // MMIO: R.4 0x23c544600 (dptx-phy[0], offset 0x4600) = 0x8000001 + read32(phy->regs[0] + 0x4600); + // MMIO: W.4 0x23c544600 (dptx-phy[0], offset 0x4600) = 0x8000003 + write32(phy->regs[0] + 0x4600, 0x8000003); + // MMIO: R.4 0x23c544600 (dptx-phy[0], offset 0x4600) = 0x8000043 + read32(phy->regs[0] + 0x4600); + // MMIO: R.4 0x23c544600 (dptx-phy[0], offset 0x4600) = 0x8000043 + read32(phy->regs[0] + 0x4600); + // MMIO: W.4 0x23c544600 (dptx-phy[0], offset 0x4600) = 0x8000041 + write32(phy->regs[0] + 0x4600, 0x8000041); + // MMIO: R.4 0x23c544408 (dptx-phy[0], offset 0x4408) = 0x482 + read32(phy->regs[0] + 0x4408); + // MMIO: W.4 0x23c544408 (dptx-phy[0], offset 0x4408) = 0x482 + write32(phy->regs[0] + 0x4408, 0x482); + // MMIO: R.4 0x23c544408 (dptx-phy[0], offset 0x4408) = 0x482 + read32(phy->regs[0] + 0x4408); + // MMIO: W.4 0x23c544408 (dptx-phy[0], offset 0x4408) = 0x483 + write32(phy->regs[0] + 0x4408, 0x483); + +#endif + + return 0; +} + +static int dptx_phy_set_active_lane_count(dptx_phy_t *phy) +{ + // MMIO: R.4 0x23c544000 (dptx-phy[0], offset 0x4000) = 0x41021ac + read32(phy->regs[0] + 0x4000); + // regs[0] + 0x4000, 0x41021ac); + // MMIO: R.4 0x23c545000 (dptx-phy[0], offset 0x5000) = 0x300 + read32(phy->regs[0] + 0x5000); + // MMIO: W.4 0x23c545000 (dptx-phy[0], offset 0x5000) = 0x300 + write32(phy->regs[0] + 0x5000, 0x300); + // MMIO: R.4 0x23c546000 (dptx-phy[0], offset 0x6000) = 0x300 + read32(phy->regs[0] + 0x6000); + // MMIO: W.4 0x23c546000 (dptx-phy[0], offset 0x6000) = 0x300 + write32(phy->regs[0] + 0x6000, 0x300); + // MMIO: R.4 0x23c547000 (dptx-phy[0], offset 0x7000) = 0x300 + read32(phy->regs[0] + 0x7000); + // MMIO: W.4 0x23c547000 (dptx-phy[0], offset 0x7000) = 0x300 + write32(phy->regs[0] + 0x7000, 0x300); + // MMIO: R.4 0x23c548000 (dptx-phy[0], offset 0x8000) = 0x300 + read32(phy->regs[0] + 0x8000); + // MMIO: W.4 0x23c548000 (dptx-phy[0], offset 0x8000) = 0x300 + write32(phy->regs[0] + 0x8000, 0x300); + // MMIO: R.4 0x23c545000 (dptx-phy[0], offset 0x5000) = 0x300 + read32(phy->regs[0] + 0x5000); + // MMIO: W.4 0x23c545000 (dptx-phy[0], offset 0x5000) = 0x300 + write32(phy->regs[0] + 0x5000, 0x300); + // >ep:28 00a2000000000280 () + // MMIO: R.4 0x23c546000 (dptx-phy[0], offset 0x6000) = 0x300 + read32(phy->regs[0] + 0x6000); + // regs[0] + 0x6000, 0x300); + // MMIO: R.4 0x23c547000 (dptx-phy[0], offset 0x7000) = 0x300 + read32(phy->regs[0] + 0x7000); + // MMIO: W.4 0x23c547000 (dptx-phy[0], offset 0x7000) = 0x300 + write32(phy->regs[0] + 0x7000, 0x300); + // MMIO: R.4 0x23c548000 (dptx-phy[0], offset 0x8000) = 0x300 + read32(phy->regs[0] + 0x8000); + // MMIO: W.4 0x23c548000 (dptx-phy[0], offset 0x8000) = 0x300 + write32(phy->regs[0] + 0x8000, 0x300); + + return 0; +} + +static int dptx_phy_set_link_rate(dptx_phy_t *phy) +{ + // MMIO: R.4 0x23c544004 (dptx-phy[0], offset 0x4004) = 0x49 + read32(phy->regs[0] + 0x4004); + // MMIO: W.4 0x23c544004 (dptx-phy[0], offset 0x4004) = 0x49 + write32(phy->regs[0] + 0x4004, 0x49); + // MMIO: R.4 0x23c544000 (dptx-phy[0], offset 0x4000) = 0x41021ac + read32(phy->regs[0] + 0x4000); + // MMIO: W.4 0x23c544000 (dptx-phy[0], offset 0x4000) = 0x41021ac + write32(phy->regs[0] + 0x4000, 0x41021ac); + // MMIO: R.4 0x23c544004 (dptx-phy[0], offset 0x4004) = 0x49 + read32(phy->regs[0] + 0x4004); + // MMIO: W.4 0x23c544004 (dptx-phy[0], offset 0x4004) = 0x41 + write32(phy->regs[0] + 0x4004, 0x41); + // MMIO: R.4 0x23c544000 (dptx-phy[0], offset 0x4000) = 0x41021ac + read32(phy->regs[0] + 0x4000); + // >ep:27 00a2000000000300 () + // MMIO: W.4 0x23c544000 (dptx-phy[0], offset 0x4000) = 0x41021ac + write32(phy->regs[0] + 0x4000, 0x41021ac); + // regs[0] + 0x4000); + // MMIO: W.4 0x23c544000 (dptx-phy[0], offset 0x4000) = 0x41021ac + write32(phy->regs[0] + 0x4000, 0x41021ac); + // MMIO: R.4 0x23c542200 (dptx-phy[0], offset 0x2200) = 0x2002 + read32(phy->regs[0] + 0x2200); + // MMIO: R.4 0x23c542200 (dptx-phy[0], offset 0x2200) = 0x2002 + read32(phy->regs[0] + 0x2200); + // MMIO: W.4 0x23c542200 (dptx-phy[0], offset 0x2200) = 0x2000 + write32(phy->regs[0] + 0x2200, 0x2000); + // MMIO: R.4 0x23c54100c (dptx-phy[0], offset 0x100c) = 0xf000 + read32(phy->regs[0] + 0x100c); + // MMIO: W.4 0x23c54100c (dptx-phy[0], offset 0x100c) = 0xf000 + write32(phy->regs[0] + 0x100c, 0xf000); + // MMIO: R.4 0x23c54100c (dptx-phy[0], offset 0x100c) = 0xf000 + read32(phy->regs[0] + 0x100c); + // MMIO: W.4 0x23c54100c (dptx-phy[0], offset 0x100c) = 0xf008 + write32(phy->regs[0] + 0x100c, 0xf008); + // MMIO: R.4 0x23c541014 (dptx-phy[0], offset 0x1014) = 0x1 + read32(phy->regs[0] + 0x1014); + // MMIO: R.4 0x23c54100c (dptx-phy[0], offset 0x100c) = 0xf008 + read32(phy->regs[0] + 0x100c); + // MMIO: W.4 0x23c54100c (dptx-phy[0], offset 0x100c) = 0xf000 + write32(phy->regs[0] + 0x100c, 0xf000); + // MMIO: R.4 0x23c541008 (dptx-phy[0], offset 0x1008) = 0x1 + read32(phy->regs[0] + 0x1008); + // MMIO: R.4 0x23c542220 (dptx-phy[0], offset 0x2220) = 0x11090a0 + read32(phy->regs[0] + 0x2220); + // MMIO: W.4 0x23c542220 (dptx-phy[0], offset 0x2220) = 0x1109020 + write32(phy->regs[0] + 0x2220, 0x1109020); + // MMIO: R.4 0x23c5420b0 (dptx-phy[0], offset 0x20b0) = 0x1e0e01c2 + read32(phy->regs[0] + 0x20b0); + // MMIO: W.4 0x23c5420b0 (dptx-phy[0], offset 0x20b0) = 0x1e0e01c2 + write32(phy->regs[0] + 0x20b0, 0x1e0e01c2); + // MMIO: R.4 0x23c5420b4 (dptx-phy[0], offset 0x20b4) = 0x7fffffe + read32(phy->regs[0] + 0x20b4); + // MMIO: W.4 0x23c5420b4 (dptx-phy[0], offset 0x20b4) = 0x7fffffe + write32(phy->regs[0] + 0x20b4, 0x7fffffe); + // MMIO: R.4 0x23c5420b4 (dptx-phy[0], offset 0x20b4) = 0x7fffffe + read32(phy->regs[0] + 0x20b4); + // MMIO: W.4 0x23c5420b4 (dptx-phy[0], offset 0x20b4) = 0x7fffffe + write32(phy->regs[0] + 0x20b4, 0x7fffffe); + // MMIO: R.4 0x23c5420b8 (dptx-phy[0], offset 0x20b8) = 0x654800 + read32(phy->regs[0] + 0x20b8); + // MMIO: W.4 0x23c5420b8 (dptx-phy[0], offset 0x20b8) = 0x654800 + write32(phy->regs[0] + 0x20b8, 0x654800); + // MMIO: R.4 0x23c5420b8 (dptx-phy[0], offset 0x20b8) = 0x654800 + read32(phy->regs[0] + 0x20b8); + // MMIO: W.4 0x23c5420b8 (dptx-phy[0], offset 0x20b8) = 0x654800 + write32(phy->regs[0] + 0x20b8, 0x654800); + // MMIO: R.4 0x23c5420b8 (dptx-phy[0], offset 0x20b8) = 0x654800 + read32(phy->regs[0] + 0x20b8); + // MMIO: W.4 0x23c5420b8 (dptx-phy[0], offset 0x20b8) = 0x654800 + write32(phy->regs[0] + 0x20b8, 0x654800); + // MMIO: R.4 0x23c5420b8 (dptx-phy[0], offset 0x20b8) = 0x654800 + read32(phy->regs[0] + 0x20b8); + // MMIO: W.4 0x23c5420b8 (dptx-phy[0], offset 0x20b8) = 0x454800 + write32(phy->regs[0] + 0x20b8, 0x454800); + // MMIO: R.4 0x23c5420b8 (dptx-phy[0], offset 0x20b8) = 0x454800 + read32(phy->regs[0] + 0x20b8); + // MMIO: W.4 0x23c5420b8 (dptx-phy[0], offset 0x20b8) = 0x454800 + write32(phy->regs[0] + 0x20b8, 0x454800); + // MMIO: R.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0x0 + read32(phy->regs[1] + 0xa0); + // MMIO: W.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0x8 + write32(phy->regs[1] + 0xa0, 0x8); + // MMIO: R.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0x8 + read32(phy->regs[1] + 0xa0); + // MMIO: W.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0xc + write32(phy->regs[1] + 0xa0, 0xc); + // MMIO: R.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0xc + read32(phy->regs[1] + 0xa0); + // MMIO: W.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0x4000c + write32(phy->regs[1] + 0xa0, 0x4000c); + // MMIO: R.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0x4000c + read32(phy->regs[1] + 0xa0); + // MMIO: W.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0xc + write32(phy->regs[1] + 0xa0, 0xc); + // MMIO: R.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0xc + read32(phy->regs[1] + 0xa0); + // MMIO: W.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0x8000c + write32(phy->regs[1] + 0xa0, 0x8000c); + // MMIO: R.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0x8000c + read32(phy->regs[1] + 0xa0); + // MMIO: W.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0xc + write32(phy->regs[1] + 0xa0, 0xc); + // MMIO: R.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0xc + read32(phy->regs[1] + 0xa0); + // MMIO: W.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0x8 + write32(phy->regs[1] + 0xa0, 0x8); + // MMIO: R.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0x8 + read32(phy->regs[1] + 0xa0); + // MMIO: W.4 0x23c5000a0 (dptx-phy[1], offset 0xa0) = 0x0 + write32(phy->regs[1] + 0xa0, 0x0); + // MMIO: R.4 0x23c542000 (dptx-phy[0], offset 0x2000) = 0x2 + read32(phy->regs[0] + 0x2000); + // MMIO: W.4 0x23c542000 (dptx-phy[0], offset 0x2000) = 0x2 + write32(phy->regs[0] + 0x2000, 0x2); + // MMIO: R.4 0x23c542018 (dptx-phy[0], offset 0x2018) = 0x0 + read32(phy->regs[0] + 0x2018); + // MMIO: W.4 0x23c542018 (dptx-phy[0], offset 0x2018) = 0x0 + write32(phy->regs[0] + 0x2018, 0x0); + // MMIO: R.4 0x23c54100c (dptx-phy[0], offset 0x100c) = 0xf000 + read32(phy->regs[0] + 0x100c); + // MMIO: W.4 0x23c54100c (dptx-phy[0], offset 0x100c) = 0xf007 + write32(phy->regs[0] + 0x100c, 0xf007); + // MMIO: R.4 0x23c54100c (dptx-phy[0], offset 0x100c) = 0xf007 + read32(phy->regs[0] + 0x100c); + // MMIO: W.4 0x23c54100c (dptx-phy[0], offset 0x100c) = 0xf00f + write32(phy->regs[0] + 0x100c, 0xf00f); + // MMIO: R.4 0x23c541014 (dptx-phy[0], offset 0x1014) = 0x38f + read32(phy->regs[0] + 0x1014); + // MMIO: R.4 0x23c54100c (dptx-phy[0], offset 0x100c) = 0xf00f + read32(phy->regs[0] + 0x100c); + // MMIO: W.4 0x23c54100c (dptx-phy[0], offset 0x100c) = 0xf007 + write32(phy->regs[0] + 0x100c, 0xf007); + // MMIO: R.4 0x23c541008 (dptx-phy[0], offset 0x1008) = 0x9 + read32(phy->regs[0] + 0x1008); + // MMIO: R.4 0x23c542200 (dptx-phy[0], offset 0x2200) = 0x2000 + read32(phy->regs[0] + 0x2200); + // MMIO: W.4 0x23c542200 (dptx-phy[0], offset 0x2200) = 0x2002 + write32(phy->regs[0] + 0x2200, 0x2002); + // MMIO: R.4 0x23c545010 (dptx-phy[0], offset 0x5010) = 0x18003000 + read32(phy->regs[0] + 0x5010); + // MMIO: W.4 0x23c545010 (dptx-phy[0], offset 0x5010) = 0x18003000 + write32(phy->regs[0] + 0x5010, 0x18003000); + // MMIO: R.4 0x23c546010 (dptx-phy[0], offset 0x6010) = 0x18003000 + read32(phy->regs[0] + 0x6010); + // MMIO: W.4 0x23c546010 (dptx-phy[0], offset 0x6010) = 0x18003000 + write32(phy->regs[0] + 0x6010, 0x18003000); + // MMIO: R.4 0x23c547010 (dptx-phy[0], offset 0x7010) = 0x18003000 + read32(phy->regs[0] + 0x7010); + // MMIO: W.4 0x23c547010 (dptx-phy[0], offset 0x7010) = 0x18003000 + write32(phy->regs[0] + 0x7010, 0x18003000); + // MMIO: R.4 0x23c548010 (dptx-phy[0], offset 0x8010) = 0x18003000 + read32(phy->regs[0] + 0x8010); + // MMIO: W.4 0x23c548010 (dptx-phy[0], offset 0x8010) = 0x18003000 + write32(phy->regs[0] + 0x8010, 0x18003000); + // MMIO: R.4 0x23c544000 (dptx-phy[0], offset 0x4000) = 0x41021ac + read32(phy->regs[0] + 0x4000); + // MMIO: W.4 0x23c544000 (dptx-phy[0], offset 0x4000) = 0x51021ac + write32(phy->regs[0] + 0x4000, 0x51021ac); + // MMIO: R.4 0x23c544000 (dptx-phy[0], offset 0x4000) = 0x51021ac + read32(phy->regs[0] + 0x4000); + // MMIO: W.4 0x23c544000 (dptx-phy[0], offset 0x4000) = 0x71021ac + write32(phy->regs[0] + 0x4000, 0x71021ac); + // MMIO: R.4 0x23c544004 (dptx-phy[0], offset 0x4004) = 0x41 + read32(phy->regs[0] + 0x4004); + // MMIO: W.4 0x23c544004 (dptx-phy[0], offset 0x4004) = 0x49 + write32(phy->regs[0] + 0x4004, 0x49); + // MMIO: R.4 0x23c544000 (dptx-phy[0], offset 0x4000) = 0x71021ac + read32(phy->regs[0] + 0x4000); + // MMIO: W.4 0x23c544000 (dptx-phy[0], offset 0x4000) = 0x71021ec + write32(phy->regs[0] + 0x4000, 0x71021ec); + // MMIO: R.4 0x23c544004 (dptx-phy[0], offset 0x4004) = 0x49 + read32(phy->regs[0] + 0x4004); + // MMIO: W.4 0x23c544004 (dptx-phy[0], offset 0x4004) = 0x48 + write32(phy->regs[0] + 0x4004, 0x48); + + return 0; +} + +int dptx_phy_configure(dptx_phy_t *phy, int state) +{ + switch (state) { + case DPTX_APCALL_ACTIVATE: + return dptx_phy_activate(phy); + case DPTX_APCALL_SET_ACTIVE_LANE_COUNT: + return dptx_phy_set_active_lane_count(phy); + case DPTX_APCALL_SET_LINK_RATE: + return dptx_phy_set_link_rate(phy); + default: + printf("DPtx-phy: ignore unkown state:%d\n", state); + return 0; + } +} + +dptx_phy_t *dptx_phy_init(const char *phy_node) +{ + int adt_phy_path[8]; + + int node = adt_path_offset_trace(adt, phy_node, adt_phy_path); + if (node < 0) { + printf("DPtx-phy: Error getting phy node %s\n", phy_node); + return NULL; + } + + dptx_phy_t *phy = calloc(sizeof *phy, 1); + if (!phy) + return NULL; + + if (adt_get_reg(adt, adt_phy_path, "reg", 0, &phy->regs[0], NULL) < 0) { + printf("DPtx-phy: failed to get %s.reg[0]\n", phy_node); + goto out_err; + } + + if (adt_get_reg(adt, adt_phy_path, "reg", 1, &phy->regs[1], NULL) < 0) { + printf("DPtx-phy: failed to get %s.reg[1]\n", phy_node); + goto out_err; + } + + return phy; + +out_err: + free(phy); + return NULL; +} + +void dptx_phy_shutdown(dptx_phy_t *phy) +{ + free(phy); +} diff --git a/src/dcp/dptxep.c b/src/dcp/dptxep.c index 828d4174..309ac0b4 100644 --- a/src/dcp/dptxep.c +++ b/src/dcp/dptxep.c @@ -5,6 +5,7 @@ #include #include "dptxep.h" +#include "dp_phy.h" #include "malloc.h" #include "parser.h" @@ -65,6 +66,7 @@ struct epic_service_call { typedef struct dcp_dptx_if { afk_epic_ep_t *epic; // ensure an afk_epic_ep_t pointer can be used as dcp_dptx_if_t dcp_dev_t *dcp; + dptx_phy_t *phy; int channel; struct dptx_port port[2]; @@ -363,6 +365,10 @@ static int dptxport_call_set_tiled_display_hint(afk_epic_service_t *service, voi static int dptxport_call(afk_epic_service_t *service, u32 idx, const void *data, size_t data_size, void *reply, size_t reply_size) { + dcp_dptx_if_t *dptx = service->intf; + if (dptx->phy) + dptx_phy_configure(dptx->phy, idx); + switch (idx) { case DPTX_APCALL_WILL_CHANGE_LINKG_CONFIG: return dptxport_call_will_change_link_config(service); @@ -460,11 +466,13 @@ static const afk_epic_service_ops_t dcp_dptx_ops = { .call = dptxport_call, }; -int dcp_dptx_connect(dcp_dptx_if_t *dptx, u32 port) +int dcp_dptx_connect(dcp_dptx_if_t *dptx, dptx_phy_t *phy, u32 port) { if (!dptx->port[port].service) return -1; + dptx->phy = phy; + // dptx->port[port].atcphy = phy; // dptxport_validate_connection(dptx->port[port].service, 0, 5, 0); dptxport_connect(dptx->port[port].service, 0, 5, 0); diff --git a/src/dcp/dptxep.h b/src/dcp/dptxep.h index 2c5b3665..90944874 100644 --- a/src/dcp/dptxep.h +++ b/src/dcp/dptxep.h @@ -4,6 +4,8 @@ #ifndef __APPLE_DCP_DPTXEP_H__ #define __APPLE_DCP_DPTXEP_H__ +#include "dp_phy.h" + #include "../dcp.h" #include "../types.h" @@ -51,7 +53,7 @@ enum dptx_link_rate { dcp_dptx_if_t *dcp_dptx_init(dcp_dev_t *dcp); int dcp_dptx_shutdown(dcp_dptx_if_t *dptx); -int dcp_dptx_connect(dcp_dptx_if_t *dptx, u32 port); +int dcp_dptx_connect(dcp_dptx_if_t *dptx, dptx_phy_t *phy, u32 port); int dcp_dptx_disconnect(dcp_dptx_if_t *dptx, u32 port); int dcp_dptx_hpd(dcp_dptx_if_t *dptx, u32 port, bool hpd); diff --git a/src/display.c b/src/display.c index bc63f667..b88b82cd 100644 --- a/src/display.c +++ b/src/display.c @@ -11,6 +11,7 @@ #include "utils.h" #include "xnuboot.h" +#include "dcp/dp_phy.h" #include "dcp/dptxep.h" #define DISPLAY_STATUS_DELAY 100 @@ -218,7 +219,8 @@ int display_start_dcp(void) return -1; } - dcp_dptx_connect(dptx, 0); + dptx_phy_t *dpphy = dptx_phy_init("/arm-io/dptx-phy"); + dcp_dptx_connect(dptx, dpphy, 0); return 0; }