m1n1.proxyutils: Support sys/sysl ops (e.g. tlbi)

Signed-off-by: Asahi Lina <lina@asahilina.net>
This commit is contained in:
Asahi Lina 2022-08-17 14:09:14 +09:00
parent 60d69697d3
commit bfccbd32e7

View file

@ -119,8 +119,8 @@ class ProxyUtils(Reloadable):
'''read system register reg'''
op0, op1, CRn, CRm, op2 = sysreg_parse(reg)
op = (((op0 & 1) << 19) | (op1 << 16) | (CRn << 12) |
(CRm << 8) | (op2 << 5) | 0xd5300000)
op = ((op0 << 19) | (op1 << 16) | (CRn << 12) |
(CRm << 8) | (op2 << 5) | 0xd5200000)
return self.exec(op, call=call, silent=silent)
@ -128,11 +128,14 @@ class ProxyUtils(Reloadable):
'''Write val to system register reg'''
op0, op1, CRn, CRm, op2 = sysreg_parse(reg)
op = (((op0 & 1) << 19) | (op1 << 16) | (CRn << 12) |
(CRm << 8) | (op2 << 5) | 0xd5100000)
op = ((op0 << 19) | (op1 << 16) | (CRn << 12) |
(CRm << 8) | (op2 << 5) | 0xd5000000)
self.exec(op, val, call=call, silent=silent)
sys = msr
sysl = mrs
def exec(self, op, r0=0, r1=0, r2=0, r3=0, *, silent=False, call=None, ignore_exceptions=False):
if callable(call):
region = REGION_RX_EL1