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https://github.com/AsahiLinux/m1n1
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Add support for handling EL3.
A7-A9X has an EL3. Handle it (without SMP support). Signed-off-by: Nick Chan <towinchenmi@gmail.com>
This commit is contained in:
Nick Chan
Hector Martin
parent
5dfb07f3da
commit
accb393510
7 changed files with 97 additions and 13 deletions
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@ -1,6 +1,7 @@
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ENTRY(_start)
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_stack_size = 0x20000;
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_stack_size_el3 = 0x8000;
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/* We are actually relocatable */
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. = 0;
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@ -71,6 +72,12 @@ SECTIONS {
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*(COMMON)
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_bss_end = .;
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} : data
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.stack_el3 : ALIGN(0x4000) {
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PROVIDE(_stack_top_el3 = .);
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. += _stack_size_el3 - 8;
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QUAD(0x5176694b43415453);
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PROVIDE(_stack_bot_el3 = .);
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}
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.stack : ALIGN(0x4000) {
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PROVIDE(_stack_top = .);
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. += _stack_size - 8;
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5
m1n1.ld
5
m1n1.ld
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@ -4,6 +4,7 @@ ENTRY(_start)
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_va_base = 0xFFFFFE0007004000;
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_stack_size = 0x20000;
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_stack_size_el3 = 0x8000;
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_max_payload_size = 64*1024*1024;
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@ -176,6 +177,10 @@ SECTIONS {
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*(COMMON)
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. = ALIGN(0x4000);
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_bss_end = .;
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PROVIDE(_stack_top_el3 = .);
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. += _stack_size_el3;
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PROVIDE(_stack_bot_el3 = .);
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. = ALIGN(0x4000);
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PROVIDE(_stack_top = .);
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. += _stack_size;
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PROVIDE(_stack_bot = .);
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@ -69,7 +69,7 @@ void init_t6021_avalanche(int rev);
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void init_t6031_sawtooth(void);
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void init_t6031_everest(int rev);
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bool cpufeat_actlr_el2;
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bool cpufeat_actlr_el2, cpufeat_fast_ipi;
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const char *init_cpu(void)
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{
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@ -30,6 +30,8 @@ static char *m_table[0x10] = {
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[0x05] = "EL1h", //
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[0x08] = "EL2t", //
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[0x09] = "EL2h", //
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[0x0c] = "EL3t", //
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[0x0d] = "EL3h", //
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};
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static char *gl_m_table[0x10] = {
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@ -114,6 +116,8 @@ static const char *get_exception_level(void)
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return "EL1";
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else if (lvl == 0x08)
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return "EL2";
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else if (lvl == 0x0c)
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return "EL3";
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}
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return "?";
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@ -121,7 +125,10 @@ static const char *get_exception_level(void)
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void exception_initialize(void)
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{
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msr(VBAR_EL1, _vectors_start);
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if (in_el3())
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msr(VBAR_EL3, _vectors_start);
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else
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msr(VBAR_EL1, _vectors_start);
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// Clear FIQ sources
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msr(CNTP_CTL_EL0, 7L);
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@ -130,9 +137,12 @@ void exception_initialize(void)
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msr(CNTP_CTL_EL02, 7L);
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msr(CNTV_CTL_EL02, 7L);
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}
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reg_clr(SYS_IMP_APL_PMCR0, PMCR0_IACT | PMCR0_IMODE_MASK);
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reg_clr(SYS_IMP_APL_UPMCR0, UPMCR0_IMODE_MASK);
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msr(SYS_IMP_APL_IPI_SR_EL1, IPI_SR_PENDING);
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if (cpufeat_fast_ipi) {
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reg_clr(SYS_IMP_APL_PMCR0, PMCR0_IACT | PMCR0_IMODE_MASK);
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reg_clr(SYS_IMP_APL_UPMCR0, UPMCR0_IMODE_MASK);
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msr(SYS_IMP_APL_IPI_SR_EL1, IPI_SR_PENDING);
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}
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if (is_boot_cpu())
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msr(DAIF, 0 << 6); // Enable SError, IRQ and FIQ
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@ -168,8 +178,10 @@ void print_regs(u64 *regs, int el12)
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u64 sp = ((u64)(regs)) + 256;
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in_gl = in_gl12();
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bool el3 = in_el3();
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u64 spsr = in_gl ? mrs(SYS_IMP_APL_SPSR_GL1) : (el12 ? mrs(SPSR_EL12) : mrs(SPSR_EL1));
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u64 spsr = in_gl ? mrs(SYS_IMP_APL_SPSR_GL1)
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: (el12 ? mrs(SPSR_EL12) : (el3 ? mrs(SPSR_EL3) : mrs(SPSR_EL1)));
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printf("Exception taken from %s\n", get_exception_source(spsr));
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printf("Running in %s\n", get_exception_level());
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@ -184,9 +196,12 @@ void print_regs(u64 *regs, int el12)
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printf("x24-x27: %016lx %016lx %016lx %016lx\n", regs[24], regs[25], regs[26], regs[27]);
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printf("x28-x30: %016lx %016lx %016lx\n", regs[28], regs[29], regs[30]);
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u64 elr = in_gl ? mrs(SYS_IMP_APL_ELR_GL1) : (el12 ? mrs(ELR_EL12) : mrs(ELR_EL1));
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u64 esr = in_gl ? mrs(SYS_IMP_APL_ESR_GL1) : (el12 ? mrs(ESR_EL12) : mrs(ESR_EL1));
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u64 far = in_gl ? mrs(SYS_IMP_APL_FAR_GL1) : (el12 ? mrs(FAR_EL12) : mrs(FAR_EL1));
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u64 elr = in_gl ? mrs(SYS_IMP_APL_ELR_GL1)
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: (el12 ? mrs(ELR_EL12) : (el3 ? mrs(ELR_EL3) : mrs(ELR_EL1)));
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u64 esr = in_gl ? mrs(SYS_IMP_APL_ESR_GL1)
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: (el12 ? mrs(ESR_EL12) : (el3 ? mrs(ESR_EL3) : mrs(ESR_EL1)));
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u64 far = in_gl ? mrs(SYS_IMP_APL_FAR_GL1)
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: (el12 ? mrs(FAR_EL12) : (el3 ? mrs(FAR_EL3) : mrs(FAR_EL1)));
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printf("PC: 0x%lx (rel: 0x%lx)\n", elr, elr - (u64)_base);
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printf("SP: 0x%lx\n", sp);
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@ -221,10 +236,11 @@ void exc_sync(u64 *regs)
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u32 insn;
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int el12 = 0;
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bool in_gl = in_gl12();
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bool el3 = in_el3();
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u64 spsr = in_gl ? mrs(SYS_IMP_APL_SPSR_GL1) : mrs(SPSR_EL1);
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u64 esr = in_gl ? mrs(SYS_IMP_APL_ESR_GL1) : mrs(ESR_EL1);
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u64 elr = in_gl ? mrs(SYS_IMP_APL_ELR_GL1) : mrs(ELR_EL1);
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u64 spsr = in_gl ? mrs(SYS_IMP_APL_SPSR_GL1) : (el3 ? mrs(SPSR_EL3) : mrs(SPSR_EL1));
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u64 esr = in_gl ? mrs(SYS_IMP_APL_ESR_GL1) : (el3 ? mrs(ESR_EL3) : mrs(ESR_EL1));
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u64 elr = in_gl ? mrs(SYS_IMP_APL_ELR_GL1) : (el3 ? mrs(ELR_EL3) : mrs(ELR_EL1));
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if ((spsr & 0xf) == 0 && ((esr >> 26) & 0x3f) == 0x3c) {
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// On clean EL0 return, let the normal exception return
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@ -256,6 +272,14 @@ void exc_sync(u64 *regs)
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printf("Unknown HVC: 0x%x\n", imm);
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break;
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}
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} else if (in_el3() && ((esr >> 26) & 0x3f) == 0x17) {
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// Monitor call
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u32 imm = mrs(ESR_EL3) & 0xffff;
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switch (imm) {
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default:
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printf("Unknown SMC: 0x%x\n", imm);
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break;
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}
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} else {
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if (!(exc_guard & GUARD_SILENT))
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printf("Exception: SYNC\n");
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@ -297,6 +321,8 @@ void exc_sync(u64 *regs)
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printf("Recovering from exception (ELR=0x%lx)\n", elr);
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if (in_gl)
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msr(SYS_IMP_APL_ELR_GL1, elr);
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if (el3)
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msr(ELR_EL3, elr);
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else
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msr(ELR_EL1, elr);
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32
src/start.S
32
src/start.S
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@ -96,11 +96,27 @@ _start:
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mov w0, '\n'
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bl debug_putc
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mrs x8, CurrentEL
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cmp x8, #0xc
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beq start_el3
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mov x0, x19
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mov x1, x20
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bl _start_c
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b .
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.globl exception_initialize
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start_el3:
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bl exception_initialize
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adrp x8, _stack_bot_el3
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mov sp, x8
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mov x0, x19
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mov x1, x20
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msr tpidr_el3, xzr
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adrp x6, _stack_bot
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adr x7, _start_c
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b el3_eret_to_el1
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.globl exc_unk
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.type exc_unk, @function
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exc_unk:
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@ -148,6 +164,22 @@ cpu_reset:
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bl _cpu_reset_c
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b .
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el3_eret_to_el1:
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adr x8, _vectors_start
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msr sctlr_el1, xzr
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mrs x8, scr_el3
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orr x8, x8, #(1<<10) // EL1 execution state is AArch64
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orr x8, x8, #(1<<0) // EL1 is non-secure
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msr scr_el3, x8
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msr elr_el3, x7 // Set EL1 entry point
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mov x8, #0x5 // EL1h
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msr spsr_el3, x8
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msr sp_el1, x6 // Set EL1 stack pointer
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eret
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.globl debug_putc
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.type debug_putc, @function
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debug_putc:
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@ -115,9 +115,13 @@ void _cpu_reset_c(void *stack)
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printf(" MPIDR: 0x%lx\n", mrs(MPIDR_EL1));
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const char *type = init_cpu();
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printf(" CPU: %s\n", type);
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printf(" Running in EL%lu\n\n", mrs(CurrentEL) >> 2);
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exception_initialize();
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if (in_el3())
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return;
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if (!is_boot_cpu())
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smp_secondary_entry();
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else
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12
src/utils.h
12
src/utils.h
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@ -342,6 +342,16 @@ static inline int in_el2(void)
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return (mrs(CurrentEL) >> 2) == 2;
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}
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static inline int in_el3(void)
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{
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return (mrs(CurrentEL) >> 2) == 3;
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}
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static inline int has_el3(void)
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{
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return !!(mrs(ID_AA64PFR0_EL1) & 0xf000);
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}
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extern int boot_cpu_idx;
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extern u64 boot_cpu_mpidr;
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static inline int is_boot_cpu(void)
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@ -438,7 +448,7 @@ struct vector_args {
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extern u32 board_id, chip_id;
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extern bool is_mac;
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extern bool cpufeat_actlr_el2;
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extern bool cpufeat_actlr_el2, cpufeat_fast_ipi;
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extern struct vector_args next_stage;
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