m1n1.hw.i2c: Add I2CRegMapDev base class

Signed-off-by: Martin Povišer <povik@protonmail.com>

proxyclient/experiments/ohmmeter.py

@@ -7,7 +7,7 @@ sys.path.append(str(pathlib.Path(__file__).resolve().parents[1]))
 from m1n1.utils import *
 from enum import IntEnum
 from m1n1.setup import *
-from m1n1.hw.i2c import I2C
+from m1n1.hw.i2c import I2C, I2CRegMapDev
 
 
 class R_IRQ_MASK1(Register8):
@@ -223,20 +223,9 @@ class CS42L84Registers(RegMap):
     ASP_TXSLOT_CH1_MSB = 0x5068, Register8
 
 
-class CS42L84:
-    def __init__(self, bus, addr):
-        self.regs = CS42L84Registers(self, 0)
-        self.bus = bus
-        self.addr = addr
-
-    def write(self, regaddr, val, width=8):
-        valbytes = val.to_bytes(width//8, byteorder="little")
-        self.bus.write_reg(self.addr, regaddr, valbytes, regaddrlen=2)
-
-    def read(self, regaddr, width=8):
-        read = self.bus.read_reg(self.addr, regaddr, width//8, regaddrlen=2)
-        return int.from_bytes(read, byteorder='little')
-
+class CS42L84(I2CRegMapDev):
+    REGMAP = CS42L84Registers
+    ADDRESSING = (0, 2)
 
 def read_devid():
     pass

proxyclient/m1n1/hw/i2c.py

@@ -135,6 +135,7 @@ class I2C:
         self.iface = u.iface
         self.base = u.adt[adt_path].get_reg(0)[0]
         self.regs = I2CRegs(u, self.base)
+        self.devs = []
 
     def clear_fifos(self):
         self.regs.CTL.set(MTR=1, MRR=1)
@@ -192,3 +193,59 @@ class I2C:
         data = self._fifo_read(nbytes)
         self.regs.CTL.set(ENABLE=0, CLK=0x4)
         return data
+
+class I2CRegMapDev:
+    REGMAP = None
+    ADDRESSING = (0, 1)
+
+    def __init__(self, bus, addr, name=None):
+        self.bus = bus
+        self.addr = addr
+        self.curr_page = None
+        self.name = name
+
+        self.paged, self.regimmbytes = self.ADDRESSING
+        if self.REGMAP is not None:
+            self.regs = self.REGMAP(self, 0)
+
+    @classmethod
+    def from_adt(cls, bus, path):
+        node = bus.u.adt[path]
+        addr = node.reg[0] & 0xff
+        return cls(bus, addr, node.name)
+
+    def _switch_page(self, page):
+        assert self.paged
+        self.bus.write_reg(self.addr, 0, bytes([page]),
+                            regaddrlen=self.regimmbytes)
+        self.curr_page = page
+
+    def _snip_regaddr(self, addr):
+        pageshift = self.regimmbytes * 8
+        page = addr >> pageshift
+        immediate = addr & ~(~0 << pageshift)
+        return (page, immediate)
+
+    def write(self, reg, val, width=8):
+        page, imm = self._snip_regaddr(reg)
+
+        if self.paged and page != self.curr_page:
+            self._switch_page(page)
+
+        valbytes = val.to_bytes(width//8, byteorder="little")
+        self.bus.write_reg(self.addr, imm, valbytes,
+                            regaddrlen=self.regimmbytes)
+
+    def read(self, reg, width=8):
+        page, imm = self._snip_regaddr(reg)
+
+        if self.paged and page != self.curr_page:
+            self._switch_page(page)
+
+        data = self.bus.read_reg(self.addr, imm, width//8,
+                                    regaddrlen=self.regimmbytes)
+        return int.from_bytes(data, byteorder='little')
+
+    def __repr__(self):
+        label = self.name or f"@ {self.addr:02x}"
+        return f"<{type(self).__name__} {label}>"