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m1n1.hw.uat: Flush TLB on changes

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Signed-off-by: Asahi Lina <lina@asahilina.net>
This commit is contained in:
Asahi Lina 2022-08-17 14:07:36 +09:00
parent 8f2530cf64
commit a76dd299a8
1 changed files with 7 additions and 0 deletions
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7
proxyclient/m1n1/hw/uat.py
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@ -435,13 +435,20 @@ class UAT(Reloadable):
assert addr in self.pt_cache
table = self.pt_cache[addr]
self.iface.writemem(addr, struct.pack(f"<{len(table)}Q", *table))
self.p.dc_civac(addr, 0x4000)
def flush_dirty(self):
inval = False
for page in self.dirty:
self.flush_pt(page)
inval = True
self.dirty.clear()
if inval:
self.u.inst("tlbi vmalle1os")
def invalidate_cache(self):
self.pt_cache = {}