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https://github.com/AsahiLinux/m1n1
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m1n1.gpiola: New module
Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin
parent
5e202ab2fe
commit
a05f68d1c8
1 changed files with 201 additions and 0 deletions
201
proxyclient/m1n1/gpiola.py
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201
proxyclient/m1n1/gpiola.py
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# SPDX-License-Identifier: MIT
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import os, sys, struct, time
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from .utils import *
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from . import asm
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from .proxy import REGION_RX_EL1
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from .sysreg import *
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class GPIOLogicAnalyzer(object):
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def __init__(self, u, node, pins, regs=[], div=1, cpu=1, on_pin_change=True):
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self.u = u
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self.p = u.proxy
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self.iface = u.iface
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self.cpu = cpu
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self.base = u.adt[node].get_reg(0)[0]
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self.node = node
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self.pins = pins
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self.regs = regs
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assert len(pins) <= 32
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assert div > 0
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self.div = div
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self.cbuf = self.u.malloc(0x1000)
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self.dbuf = None
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self.on_pin_change = on_pin_change
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self.p.mmu_init_secondary(cpu)
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self.tfreq = u.mrs(CNTFRQ_EL0)
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def start(self, ticks, bufsize=0x10000):
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self.bufsize = bufsize
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if self.dbuf:
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self.u.free(self.dbuf)
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self.dbuf = self.u.malloc(bufsize)
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text = f"""
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trace:
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add x3, x3, x2
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mov x10, x2
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mov x6, #-1
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mov x7, #0
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ldr x8, ={self.base}
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mrs x4, CNTPCT_EL0
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isb
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1:
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add x4, x4, x1
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2:
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mrs x5, CNTPCT_EL0
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isb
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cmp x5, x4
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b.lo 2b
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"""
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for idx, pin in enumerate(self.pins.values()):
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text += f"""
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ldr w9, [x8, #{pin * 4}]
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bfi x7, x9, #{idx}, #1
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"""
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if self.on_pin_change:
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text += f"""
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cmp x7, x6
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b.eq 3f
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mov x6, x7
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"""
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text += f"""
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str w5, [x2], #4
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str w7, [x2], #4
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"""
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for reg in self.regs.values():
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if isinstance(reg, tuple):
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reg = reg[0]
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text += f"""
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ldr x9, ={reg}
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ldr w9, [x9]
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str w9, [x2], #4
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"""
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text += f"""
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cmp x2, x3
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b.hs 2f
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3:
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sub x0, x0, #1
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cbnz x0, 1b
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2:
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sub x0, x2, x10
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ret
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"""
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code = asm.ARMAsm(text, self.cbuf)
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self.iface.writemem(self.cbuf, code.data)
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self.p.dc_cvau(self.cbuf, len(code.data))
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self.p.ic_ivau(self.cbuf, len(code.data))
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self.p.smp_call(self.cpu, code.trace | REGION_RX_EL1, ticks, self.div, self.dbuf, bufsize - (8 + 4 * len(self.regs)))
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def complete(self):
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wrote = self.p.smp_wait(self.cpu)
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assert wrote <= self.bufsize
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data = self.iface.readmem(self.dbuf, wrote)
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self.u.free(self.dbuf)
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self.dbuf = None
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stride = 2 + len(self.regs)
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#chexdump(data)
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self.data = [struct.unpack("<" + "I" * stride,
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data[i:i + 4 * stride])
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for i in range(0, len(data), 4 * stride)]
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def vcd(self):
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off = self.data[0][0]
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if len(self.data) > 1:
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off2 = max(0, ((self.data[1][0] - off) & 0xffffffff) - 5000)
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else:
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off2 = 0
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print(off, off2)
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vcd = []
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vcd.append("""
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$timescale 1ns $end
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$scope module gpio $end
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""")
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sym = 0
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keys = []
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rkeys = []
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for name in self.pins:
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keys.append(f"s{sym}")
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vcd.append(f"$var wire 1 s{sym} {name} $end\n")
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sym += 1
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for name, reg in self.regs.items():
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vcd.append(f"$var reg 32 s{sym} {name} [31:0] $end\n")
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if isinstance(reg, tuple):
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subkeys = {}
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rcls = reg[1]
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rkeys.append((f"s{sym}", rcls, subkeys))
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sym += 1
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for fname in rcls().fields.keys():
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fdef = getattr(rcls, fname)
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if isinstance(fdef, tuple):
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width = fdef[0] - fdef[1] + 1
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else:
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width = 1
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vcd.append(f"$var reg {width} s{sym} {name}.{fname} [{width-1}:0] $end\n")
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subkeys[fname] = (width, f"s{sym}")
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sym += 1
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else:
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rkeys.append((f"s{sym}", None, None))
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sym += 1
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vcd.append("""
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$enddefinitions $end
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$dumpvars
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""")
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for v in self.data:
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ts = v[0]
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val = v[1]
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regs = v[2:]
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ts = ((ts - off) & 0xffffffff) - off2
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ns = max(0, 1000000000 * ts // self.tfreq)
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vcd.append(f"#{ns}\n")
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vcd.append("\n".join(f"{(val>>i) & 1}{k}" for i, k in enumerate(keys)) + "\n")
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for (key, rcls, subkeys), v in zip(rkeys, regs):
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vcd.append(f"b{v:032b} {key}\n")
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if rcls:
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rval = rcls(v)
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for field, (width, key) in subkeys.items():
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v = getattr(rval, field)
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vcd.append(f"b{v:0{width}b} {key}\n")
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ns += 10000
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vcd.append(f"#{ns}\n" + "\n".join(f"{(val>>i) & 1}{k}" for i, k in enumerate(keys)) + "\n")
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return "".join(vcd)
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def show(self):
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with open("/tmp/dump.vcd", "w") as fd:
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fd.write(self.vcd())
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gtkw = ("""
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[dumpfile] "/tmp/dump.vcd"
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[timestart] 0
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[size] 3063 1418
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[pos] -1 -1
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*-17.000000 2 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[sst_width] 288
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[signals_width] 197
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[sst_expanded] 1
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[sst_vpaned_height] 421
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@23
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""" +
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"\n".join("gpio." + k for k in self.pins) + "\n" +
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"\n".join("gpio." + k + "[31:0]" for k in self.regs) + "\n")
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with open("/tmp/dump.gtkw", "w") as fd:
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fd.write(gtkw)
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os.system("gtkwave /tmp/dump.gtkw")
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